Peter Poplavko

Orcid: 0000-0002-8363-2008

According to our database1, Peter Poplavko authored at least 27 papers between 2003 and 2020.

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Bibliography

2020
Correction to: Correct-by-construction model-based design of reactive streaming software for multi-core embedded systems.
Int. J. Softw. Tools Technol. Transf., 2020

Correct-by-construction model-based design of reactive streaming software for multi-core embedded systems.
Int. J. Softw. Tools Technol. Transf., 2020

2019
Priority-based scheduling of mixed-critical jobs.
Real Time Syst., 2019

2018
Maximal software execution time: a regression-based approach.
Innov. Syst. Softw. Eng., 2018

DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems.
Des. Autom. Embed. Syst., 2018

Process Network Models for Embedded System Design Based on the Real-Time BIP Execution Engine.
Proceedings of the 1st International Workshop on Methods and Tools for Rigorous System Design, 2018

Algorithmic Complexity of Correctness Testing in MC-Scheduling.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

Predictability in Mixed-Criticality Systems.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

A Process Network Model for Reactive Streaming Software with Deterministic Task Parallelism.
Proceedings of the Fundamental Approaches to Software Engineering, 2018

2017
Regression-Based Statistical Bounds on Software Execution Time.
Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2017

Design of Embedded Systems with Complex Task Dependencies and Shared Resource Interference (Short Paper).
Proceedings of the Software Engineering and Formal Methods - 15th International Conference, 2017

2016
Mixed-Critical Systems Design with Coarse-Grained Multi-core Interference.
Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques, 2016

2015
A Timed-Automata Based Middleware for Time-Critical Multicore Applications.
Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2015

Multiprocessor Scheduling of Precedence-constrained Mixed-Critical Jobs.
Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015

Time-Triggered Mixed-Critical Scheduler on Single and Multi-processor Platforms.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Models for deterministic execution of real-time multiprocessor applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Many-Core Scheduling of Data Parallel Applications Using SMT Solvers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Symmetry Breaking for Multi-criteria Mapping and Scheduling on Multicores.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2013

Mixed Critical Earliest Deadline First.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013

2012
SPDF: A schedulable parametric data-flow MoC.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010
Predicting the throughput of multiprocessor applications under dynamic workload.
Proceedings of the 28th International Conference on Computer Design, 2010

2007
Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2005
Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

2004
Predictable Embedded Multiprocessor System Design.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

2003
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip.
Proceedings of the International Conference on Compilers, 2003

Guaranteeing the Quality of Services in Networks on Chip.
Proceedings of the Networks on Chip, 2003


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