Peter Pöchmüller

According to our database, Peter Pöchmüller authored at least 14 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Semiconductor Application Fail Root Causes And Secure Test Remedy.

Heguo Yin, Peter Poechmueller

Proceedings of the IEEE European Test Symposium, 2024

2023

A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads.

Ranran Zhou, Haozhe Wang, Peng Wang, Peter Poechmueller, Yong Wang

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

2022

An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm.

Ranran Zhou, Peter Poechmueller, Yong Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

1999

A 390-mm², 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.

Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman

IEEE J. Solid State Circuits, 1999

1996

A 286 mm² 256 Mb DRAM with ×32 both-ends DQ.

Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii

IEEE J. Solid State Circuits, 1996

Fault-tolerant designs for 256 Mb DRAM.

Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao

IEEE J. Solid State Circuits, 1996

1993

Algorithmische Synthesetransformationen und deren Anwendung auf programmierbare Architekturen in mechatronischen Systemen.

Peter Pöchmüller

PhD thesis, 1993

High-level synthesis transformations for programmable architectures.

Peter Poechmueller, Manfred Glesner, Fang Longsen

Proceedings of the European Design Automation Conference 1993, 1993

1992

High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.

Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen

Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

High-level synthesis in a rapid-prototype environment for mechatronic systems.

Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner

Proceedings of the conference on European design automation, 1992

1991

A New Approach for Designing Fault-Tolerant Array Processors.

Peter Poechmueller, Manfred Glesner

Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

A CAD tool for designing large, fault-tolerant VLSI arrays.

Peter Poechmueller, G. K. Sharma, Manfred Glesner

Proceedings of the First Great Lakes Symposium on VLSI, 1991

HADES-high-level architecture development and exploration system.

Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner

Proceedings of the First Great Lakes Symposium on VLSI, 1991

An approach for multilevel logic cell optimization in module generators.

Peter Poechmueller, Manfred Glesner

Proceedings of the First Great Lakes Symposium on VLSI, 1991