Peter M. Kelly
According to our database1,
Peter M. Kelly
authored at least 27 papers
between 1977 and 2011.
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Bibliography
2011
Trans. High Perform. Embed. Archit. Compil., 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
2009
Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
2008
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Neurocomputing, 2007
Analog Spiking Neuron with Charge-Coupled Synapses.
Proceedings of the World Congress on Engineering, 2007
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007
Proceedings of the International Joint Conference on Neural Networks, 2007
2006
A Silicon Synapse Based on a Charge Transfer Device for Spiking Neural Network Application.
Proceedings of the Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28, 2006
Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling.
Proceedings of the International Joint Conference on Neural Networks, 2006
On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses.
Proceedings of the International Joint Conference on Neural Networks, 2006
Proceedings of the Artificial Neural Networks, 2006
Proceedings of the Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 2006
Proceedings of the proceedings of the Fourth Australasian Symposium on Grid Computing and e-Research (AusGrid 2006) and the Fourth Australasian Information Security Workshop (Network Security) (AISW 2006), 2006
2005
A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005
Proceedings of the First International Conference on e-Science and Grid Technologies (e-Science 2005), 2005
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Architectural requirements for threshold logic gates based on resonant tunneling devices.
Proceedings of the IEEE International Joint Conference on Neural Networks, 2004
2003
J. Multiple Valued Log. Soft Comput., 2003
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
1977
IEEE Trans. Commun., 1977