Peter Gregorius

According to our database, Peter Gregorius authored at least 9 papers between 2004 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Hardware architecture of an Internet Protocol Version 6 processor.

Boris Traskov, Ulrich Langenbach, Klaus Hofmann, Peter Gregorius

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform.

Ulrich Langenbach, A. Berthe, Boris Traskov, S. Weide, Klaus Hofmann, Peter Gregorius

Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013

Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems.

Ashok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Adaptive Equalizer Training for High-Speed Low-Power Communication Systems.

Yuan Fang, Ling Chen, Ashok Jaiswal, Klaus Hofmann, Peter Gregorius

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2010

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

IEEE J. Solid State Circuits, 2010

2009

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

Cascading Techniques for a High-Speed Memory Interface.

Zheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Jürgen Zielbauer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS.

Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi

IEEE J. Solid State Circuits, 2005

2004

A low jitter triple-band digital LC PLL in 130nm CMOS.

Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi

Proceedings of the 33rd European Solid-State Circuits Conference, 2004