Péter Földesy
According to our database1,
Péter Földesy
authored at least 20 papers
between 1997 and 2020.
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Bibliography
2020
Non-Contact Vital-Sign Monitoring System for Premature Infants in Neonatal Intensive Care Units.
ERCIM News, 2020
Multi-Level Optimization for Enabling Life Critical Visual Inspections of Infants in Resource Limited Environment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2013
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips.
J. Syst. Archit., 2013
2012
Characterization of silicon field effect transistor sub-THz detectors for imaging systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
Int. J. Circuit Theory Appl., 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Int. J. Circuit Theory Appl., 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Proceedings of the IEEE International Joint Conference on Neural Networks, 2004
2003
J. Circuits Syst. Comput., 2003
PDE-Based Histogram Modification With Embedded Morphological Processing Of The Level-Sets.
J. Circuits Syst. Comput., 2003
2002
Int. J. Circuit Theory Appl., 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1997
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage.
IEEE J. Solid State Circuits, 1997