Peter Figuli

Affiliations:
  • Karlsruhe Institute of Technology, Germany


According to our database1, Peter Figuli authored at least 15 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
AI accelerator on IBM telum processor: industrial product.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2017
A reconfigurable high-speed spiral FIR filter architecture.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

Parameter Sensitivity in Virtual FPGA Architectures.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography.
IEEE Trans. Parallel Distributed Syst., 2016

A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing.
Proceedings of the 39th International Conference on Telecommunications and Signal Processing, 2016

2015
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Parametric design space exploration for optimizing QAM based high-speed communication.
Proceedings of the 2015 IEEE/CIC International Conference on Communications in China, 2015

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2013
JITPR: A framework for supporting fast application's implementation onto FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2013

ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores.
Proceedings of the 2013 International Symposium on System on Chip, 2013

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011


  Loading...