Peter Duzy

According to our database1, Peter Duzy authored at least 5 papers between 1990 and 1994.

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Bibliography

1994
Scheduling of behavioral VHDL by retiming techniques.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
The Siemens high-level synthesis system CALLAS.
IEEE Trans. Very Large Scale Integr. Syst., 1993

The CALLAS synthesis system and its application to mechatronic ASIC design problems.
Proceedings of the European Design Automation Conference 1993, 1993

1992
High-Level Synthesis from VHDL with Exact Timing Constraints.
Proceedings of the 29th Design Automation Conference, 1992

1990
ASIC design using the high-level synthesis system CALLAS: a case study.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990


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