Peter Debacker
Orcid: 0000-0003-3825-5554
According to our database1,
Peter Debacker
authored at least 40 papers
between 2005 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
IEEE J. Solid State Circuits, 2023
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays.
Proceedings of the IEEE International Memory Workshop, 2023
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge.
Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022
2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2019
CoRR, 2019
Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2017
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications.
J. Signal Process. Syst., 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
2013
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited).
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
2012
J. Low Power Electron., 2012
2009
Proceedings of the 6th Workshop on Positioning, Navigation and Communication, 2009
2005
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005