Peter Celinski

According to our database, Peter Celinski authored at least 7 papers between 2000 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2004

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.

Peter Celinski, Derek Abbott, Sorin Cotofana

Proceedings of the Integrated Circuit and System Design, 2004

Hybrid Parallel Counters - Domino and Threshold Logic.

Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.

Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.

Peter Celinski, Sorin Cotofana, Derek Abbott

Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

Area efficient, high speed parallel counter circuits using charge recycling threshold logic.

Peter Celinski, Derek Abbott, Sorin Dan Cotofana

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Low depth carry lookahead addition using charge recycling threshold logic.

Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000

Delay analysis of neuron-MOS and capacitive threshold-logic.

Peter Celinski, Said F. Al-Sarawi, Derek Abbott

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000