Peter C. Maxwell
Affiliations:- ON Semiconductor, USA
- Aptina Imaging, San Jose, CA, USA
- Micron Technology Inc., USA
- Agilent Technologies, Santa Clara, CA, USA
- Hewlett-Packard Company, Santa Clara, CA, USA
- University of New South Wales, Sydney, NSW, Australia
According to our database1,
Peter C. Maxwell
authored at least 45 papers
between 1974 and 2021.
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Bibliography
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2018
Proceedings of the IEEE International Test Conference, 2018
2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
Proceedings of the 21th IEEE European Test Symposium, 2016
2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Proceedings of the 16th European Test Symposium, 2011
2010
2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 12th European Test Symposium, 2007
2006
Proceedings of the 2006 IEEE International Test Conference, 2006
2003
IEEE Des. Test Comput., 2003
2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
1997
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
1995
Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
1993
IEEE Des. Test Comput., 1993
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1992
IDDQ testing as a component of a test suite: The need for several fault coverage metrics.
J. Electron. Test., 1992
The Effectiveness of I<sub>DDQ</sub>, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
1990
Proceedings of the European Design Automation Conference, 1990
1988
Comparative Analysis of Different Implementations of Multiple-Input Signature Analyzers.
IEEE Trans. Computers, 1988
1978
1977
Correct DDA Register Transfers for Trapezoidal Integration When Solving Nonlinear Equations of the Form <i>y = A y<sup>n</sup></i>.
IEEE Trans. Computers, 1977
1976
Incremental Computer Systems.
Aust. Comput. J., 1976
1974