Peter Buchmann
According to our database1,
Peter Buchmann
authored at least 27 papers
between 1987 and 2016.
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Bibliography
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth.
IEEE J. Solid State Circuits, 2014
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm<sup>2</sup> at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation.
Proceedings of the IEEE International Conference on Acoustics, 2014
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os.
Proceedings of the ESSCIRC 2014, 2014
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
2013
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS.
IEEE J. Solid State Circuits, 2013
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS.
IEEE J. Solid State Circuits, 2009
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2009
2008
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth.
IEEE J. Solid State Circuits, 2008
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
2005
A 0.94-ps-RMS-jitter 0.016-mm<sup>2</sup> 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links.
IEEE J. Solid State Circuits, 2005
2001
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution.
IEEE J. Solid State Circuits, 2001
2000
1998
Reproduction of Hypermedia Lectures.
Proceedings of WebNet 98, 1998
1987
GaAs Komponenten der Integrierten Optik für die externe Modulation in optischen Kommunikationssystemen.
PhD thesis, 1987