Peter Bennett

Affiliations:

Cadence Design Systems Inc., San Jose, CA, USA

According to our database¹, Peter Bennett authored at least 2 papers between 2006 and 2013.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Bibliography

2013

Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples.

[BibT_eX]

[DOI]

Frank Martin

Peter Bennett

Proceedings of the Design, Automation and Test in Europe, 2013

2006

A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

Peter Bennett

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Bibliography

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