Peter A. Milder

Orcid: 0000-0003-1146-3011

According to our database1, Peter A. Milder authored at least 54 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Wireless Multicast Rate Control Adaptive to Application Goodput and Loss Requirements.
Proceedings of the Ninth IEEE/ACM International Conference on Internet-of-Things Design and Implementation, 2024

2023
Efficient Methods for Natural Language Processing: A Survey.
Trans. Assoc. Comput. Linguistics, 2023

Waverunner: An Elegant Approach to Hardware Acceleration of State Machine Replication.
Proceedings of the 20th USENIX Symposium on Networked Systems Design and Implementation, 2023

Precision and Performance-Aware Voltage Scaling in DNN Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Guest Editorial: IEEE TC Special Issue: Hardware Acceleration of Machine Learning.
IEEE Trans. Computers, 2022

Efficient Methods for Natural Language Processing: A Survey.
CoRR, 2022

OPSEL: optimal producer selection under data redundancy in wireless edge environments.
Proceedings of the 9th ACM Conference on Information-Centric Networking, 2022

2021
Practical Model Checking on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2021

Unifying Address and Name Based Communication in Wireless Medium Access Control.
Proceedings of the 2021 IEEE Military Communications Conference, 2021

Aletheia: A Lightweight Tool for WiFi Medium Analysis on The Edge.
Proceedings of the ICC 2021, 2021

On the Distribution, Sparsity, and Inference-time Quantization of Attention Values in Transformers.
Proceedings of the Findings of the Association for Computational Linguistics: ACL/IJCNLP 2021, 2021

2020
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Pub/Sub in the Air: A Novel Data-centric Radio Supporting Robust Multicast in Edge Environments.
Proceedings of the 5th IEEE/ACM Symposium on Edge Computing, 2020

FPGA-Accelerated Samplesort for Large Data Sets.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Argus: An End-to-End Framework for Accelerating CNNs on FPGAs.
IEEE Micro, 2019

Runtime-Programmable Pipelines for Model Checkers on FPGAs.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Sorting Large Data Sets with FPGA-Accelerated Samplesort.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
Data Flow Oriented Hardware Design of RNS-based Polynomial Multiplication for SHE Acceleration.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Poster: A Raspberry Pi Based Data-Centric MAC for Robust Multicast in Vehicular Network.
Proceedings of the 24th Annual International Conference on Mobile Computing and Networking, 2018

Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

FPGASwarm: High Throughput Model Checking on FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Quantifying Energy and Latency Improvements of FPGA-Based Sensors for Low-Cost Spectrum Monitoring.
Proceedings of the 2018 IEEE International Symposium on Dynamic Spectrum Access Networks, 2018

2017
Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression.
ACM Trans. Embed. Comput. Syst., 2017

Maximizing CNN Accelerator Efficiency Through Resource Partitioning.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Practical Matlab experience in lecture-based signals and systems courses.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
Streaming Sorting Networks.
ACM Trans. Design Autom. Electr. Syst., 2016

Fused-layer CNN accelerators.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

MEMOCODE 2016 design contest: K-means clustering.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Overcoming resource underutilization in spatial CNN accelerators.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
MEMOCODE 2015 design contest: Continuous skyline computation.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Nautilus: fast automated IP design space search using guided genetic algorithms.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Blind symbol synchronisation in direct-detection optical OFDM using virtual subcarriers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

MEMOCODE 2014 design contest: k-Nearest Neighbors with Mahalanobis distance metric.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Trade-offs in execution signature compression for reliable processor systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Computer Generation of Hardware for Linear Digital Signal Processing Transforms.
ACM Trans. Design Autom. Electr. Syst., 2012

"Smart" design space sampling to predict Pareto-optimal solutions.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

Improving fixed-point accuracy of FFT cores in O-OFDM systems.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Computer generation of streaming sorting networks.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Hardware implementation of the discrete fourier transform with non-power-of-two problem size.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
Permuting streaming data using RAMs.
J. ACM, 2009

Automatic generation of streaming datapaths for arbitrary fixed permutations.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Domain-specific library generation for parallel software and hardware platforms.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Formal datapath representation and manipulation for implementing DSP transforms.
Proceedings of the 45th Design Automation Conference, 2008

2007
FFT Compiler: from math to efficient hardware HLDVT invited short paper.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Generating FPGA-Accelerated DFT Libraries.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Fast and accurate resource estimation of automatically generated custom DFT IP cores.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
Automatic generation of customized discrete fourier transform IPs.
Proceedings of the 42nd Design Automation Conference, 2005


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