Peter A. Ivey

According to our database1, Peter A. Ivey authored at least 17 papers between 1988 and 2004.

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Bibliography

2004
Improving accuracy, robustness and computational efficiency in 3D computer vision.
Image Vis. Comput., 2004

Performance analysis of integrated voice and multiple classes of data with a finite number of sessions.
Eur. Trans. Telecommun., 2004

2002
Continuous and high coverage self-testing of dynamically re-configurable systems.
Parallel Comput., 2002

Analytic performance of a random access protocol with mixed services of voice and a finite number of data sessions in mobile cellular networks.
Proceedings of The Fourth IEEE Conference on Mobile and Wireless Communications Networks, 2002

2001
QoS analysis in mobile cellular networks supporting voice and class of finite sessions.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

1999
Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL.
Proceedings of the VLSI: Systems on a Chip, 1999

1996
A Generalized Computer Vision Chip.
Real Time Imaging, 1996

Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technolog.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
An array processor for general purpose digital image compression.
IEEE J. Solid State Circuits, March, 1995

A single chip video signal processing architecture for image processing, coding, and computer vision.
IEEE Trans. Circuits Syst. Video Technol., 1995

1994
A 1.2 Billion Operations per Second Video Signal Processing Chip.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

A General Purpose, Single Chip Video Signal Processing (VSP) Architecture for Image Processing, Coding and Computer Vision.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

Defect Tolerant SRAM Based FPGAs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Correlation Chip for Stereo Vision.
Proceedings of the British Machine Vision Conference, 1994

Mapping Algorithms on to Platforms: An Approach to Algorithm and Hardware Co-Design.
Proceedings of the British Machine Vision Conference, 1994

1989
A single-chip public key encryption subsystem.
IEEE J. Solid State Circuits, August, 1989

1988
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung.
Proceedings of the GI, 1988


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