Perrine Batude

According to our database1, Perrine Batude authored at least 27 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024


2022
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Inter-tier Coupling Analysis in Back-illuminated Monolithic 3DSI Image Sensor Pixels.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

2020
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Advanced 3D Technologies and Architectures for 3D Smart Image Sensors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.
Proceedings of the 47th European Solid-State Device Research Conference, 2017


2016


Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Towards high density 3D interconnections.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Intermediate BEOL process influence on power and performance for 3DVLSI.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

3D FPGA using high-density interconnect Monolithic Integration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Cell transformations and physical design techniques for 3D monolithic integrated circuits.
ACM J. Emerg. Technol. Comput. Syst., 2013

2012
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Analytical modeling of parasitics in monolithically integrated 3D inverters.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Performance analysis of 3-D monolithic integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
System on Wafer: A New Silicon Concept in SiP.
Proc. IEEE, 2009


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