Per Larsson-Edefors

According to our database, Per Larsson-Edefors authored at least 108 papers between 1996 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype.

Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

Real-Time Implementation of Machine-Learning DSP.

Erik Börjeson, Keren Liu, Christian Häger, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers.

Erik Börjeson, Ekaterina Deriushkina, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

Unfolded SiBM BCH Decoders for High- Throughput Low-Latency Applications.

Xu Wang, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524 km of Live Aerial Fiber.

Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training.

Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2022

Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers.

Mikael Mazur, Roland Ryf, Nicolas K. Fontaine, Andrea Marotta, Erik Börjeson, Lauren Dallachiesa, Haoshuo Chen, Tetsuya Hayashi, Takuji Nagashima, Tetsuya Nakanishi, Tetsu Morishima, Fabio Graziosi, Luca Palmieri, David T. Neilson, Per Larsson-Edefors, Antonio Mecozzi, Cristian Antonelli

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Real-Time Transmission over 2×55 km All 7-Core Coupled-Core Multi-Core Fiber Link.

Mikael Mazur, Lauren Dallachiesa, Nicolas K. Fontaine, Roland Ryf, Erik Börjeson, Haoshuo Chen, Hirotaka Sakuma, Takafumi Ohtsuka, Tetsuya Hayashi, Takemi Hasegawa, Hidehisa Tazawa, David T. Neilson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Transoceanic Phase and Polarization Fiber Sensing using Real-Time Coherent Transceiver.

Mikael Mazur, Jorge C. Castellanos, Roland Ryf, Erik Börjeson, Tracy Chodkiewicz, Valey Kamalov, Shuang Yin, Nicolas K. Fontaine, Haoshuo Chen, Lauren Dallachiesa, Steve Corteselli, Philip Copping, Jürgen Gripp, Aurelien Mortelette, Benoit Kowalski, Rodney Dellinger, David T. Neilson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP.

Per Larsson-Edefors, Erik Börjeson

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs.

Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson, Per Larsson-Edefors

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

2021

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder.

Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems.

Erik Börjeson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2020

ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers.

Christoffer Fougstedt, Oscar Gustafsson, Cheolyong Bae, Erik Börjeson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations.

Erik Börjeson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019

Hardware Considerations for Selection Networks.

Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Energy-Efficient Soft-Assisted Product Decoders.

Christoffer Fougstedt, Alireza Sheikh, Alexandre Graell i Amat, Gianluigi Liva, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems.

Erik Börjeson, Christoffer Fougstedt, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication.

Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Custom versus Cell-Based ASIC Design for Many-Channel Correlators.

Erik Ryman, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Energy-Efficient High-Throughput Staircase Decoders.

Christoffer Fougstedt, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI.

Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels.

Lars Lundberg, Erik Börjeson, Christoffer Fougstedt, Mikael Mazur, Magnus Karlsson, Peter A. Andrekson, Per Larsson-Edefors

Proceedings of the European Conference on Optical Communication, 2018

ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters.

Christoffer Fougstedt, Christian Häger, Lars J. Svensson, Henry D. Pfister, Per Larsson-Edefors

Proceedings of the European Conference on Optical Communication, 2018

2017

A framework for a relative real-time tracking system based on ultra-wideband technology.

Gabriel Ortiz, Fredrik Treven, Lars J. Svensson, Per Larsson-Edefors, Sebastian Johansson-Mauricio

Proceedings of the 14th Workshop on Positioning, Navigation and Communications, 2017

Time-domain digital back propagation: Algorithm and finite-precision implementation aspects.

Christoffer Fougstedt, Mikael Mazur, Lars J. Svensson, Henrik Eliasson, Magnus Karlsson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry.

Erik Ryman, Anders Emrich, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization.

Christoffer Fougstedt, Lars J. Svensson, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors

Proceedings of the European Conference on Optical Communication, 2017

Improved Low-Power LDPC FEC for Coherent Optical Systems.

Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson

Proceedings of the European Conference on Optical Communication, 2017

Instruction level energy model for the Adapteva Epiphany multi-core processor.

Gabriel Ortiz, Lars J. Svensson, Erik Alveflo, Per Larsson-Edefors

Proceedings of the Computing Frontiers Conference, 2017

2016

Dynamic equalizer power dissipation optimization.

Christoffer Fougstedt, Pontus Johannisson, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Logic filter cache for wide-VDD-range processors.

Alen Bardizbanyan, Oskar Andersson, Joachim Neves Rodrigues, Per Larsson-Edefors

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Practical way halting by speculatively accessing halt tags.

Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Redesigning a tagless access buffer to require minimal ISA changes.

Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores.

Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Exploring early and late ALUs for single-issue in-order pipelines.

Alen Bardizbanyan, Per Larsson-Edefors

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Impact of forward error correction on energy consumption of VCSEL-based transmitters.

Krzysztof Szczerba, Christoffer Fougstedt, Per Larsson-Edefors, Petter Westbergh, Alexandre Graell i Amat, Lars J. Svensson, Magnus Karlsson, Anders Larsson, Peter A. Andrekson

Proceedings of the European Conference on Optical Communication, 2015

Energy-efficient soft-decision LDPC FEC For long-haul optical communication.

Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson

Proceedings of the European Conference on Optical Communication, 2015

2014

1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis.

Erik Ryman, Anders Emrich, Stefan Back Andersson, Lars J. Svensson, Per Larsson-Edefors

IEEE J. Solid State Circuits, 2014

Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications.

Fredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration.

Per Larsson-Edefors, Kjell O. Jeppson

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD³).

Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Designing a practical data filter cache to improve both energy efficiency and performance.

Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors

ACM Trans. Archit. Code Optim., 2013

FlexCore: Implementing an exposed datapath processor.

Magnus Själander, Per Larsson-Edefors

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment.

Kjell O. Jeppson, Per Larsson-Edefors

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Manufacturable nanometer designs using standard cells with regular layout.

Kasyab P. Subramaniyan, Per Larsson-Edefors

Proceedings of the International Symposium on Quality Electronic Design, 2013

A SiGe 8-channel comparator for application in a synthetic aperture radiometer.

Erik Ryman, Stefan Back Andersson, J. Riesbeck, S. Dejanovic, Anders Emrich, Per Larsson-Edefors

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Speculative tag access for reduced energy dissipation in set-associative L1 data caches.

Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Improving data access efficiency by using a tagless access buffer (TAB).

Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012

Configurable RTL model for level-1 caches.

Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Data-Width-Driven Power Gating of Integer Arithmetic Circuits.

Tung Thanh Hoang, Per Larsson-Edefors

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers.

Fredrik Toft, Niclas Rousk, Jonas Mårtensson, Marco Forzati, Bengt-Erik Olsson, Per Larsson-Edefors

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Viterbi Accelerator for Embedded Processor Datapaths.

Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect.

Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor.

Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry.

Erik Ryman, Anders Emrich, Stefan Back Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.

Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters.

Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

On-chip power supply noise and its implications on timing.

Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.

Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Design space exploration for an embedded processor with flexible datapath interconnect.

Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.

Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström

J. Signal Process. Syst., 2009

Multiplication Acceleration Through Twin Precision.

Magnus Själander, Per Larsson-Edefors

IEEE Trans. Very Large Scale Integr. Syst., 2009

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.

Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Scheduling for an Embedded Architecture with a Flexible Datapath.

Thomas Schilling, Magnus Själander, Per Larsson-Edefors

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.

Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Layout exploration of geometrically accurate arithmetic circuits.

Kasyab P. Subramaniyan, Emil Axelsson, Per Larsson-Edefors, Mary Sheeran

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree.

Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Time-domain interconnect characterisation flow for appropriate model segmentation.

Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors

IET Comput. Digit. Tech., 2008

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach.

Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Noise Interaction Between Power Distribution Grids and Substrate.

Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.

Magnus Själander, Per Larsson-Edefors

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A Flexible Datapath Interconnect for Embedded Applications.

Magnus Själander, Per Larsson-Edefors, Magnus Björk

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Overdrive Power-Gating Techniques for Total Power Minimization.

Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.

Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert

IEEE Trans. Very Large Scale Integr. Syst., 2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Multiplier reduction tree with logarithmic logic depth and regular connectivity.

Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A low-leakage twin-precision multiplier using reconfigurable power gating.

Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accounting for the skin effect during repeater insertion.

Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

On Maximum Current Estimation in CMOS Digital Circuits.

Dainius Ciuplys, Per Larsson-Edefors

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.

Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson

Proceedings of the Integrated Circuit and System Design, 2004

On Skin Effect in On-Chip Interconnects.

Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the Integrated Circuit and System Design, 2004

Dynamic pass-transistor dot operators for efficient parallel-prefix adders.

Henrik Eriksson, Per Larsson-Edefors

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Glitch-conscious low-power design of arithmetic circuits.

Henrik Eriksson, Per Larsson-Edefors

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Evaluation of power cut-off techniques in the presence of gate leakage.

Mindaugas Drazdziulis, Per Larsson-Edefors

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Efficient Twin-Precision Multiplier.

Magnus Själander, Henrik Eriksson, Per Larsson-Edefors

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A power cut-off technique for gate leakage suppression [CMOS logic circuits].

Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects.

Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Mixed-Mode Delay-Locked-Loop Architecture.

Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A gate leakage reduction strategy for future CMOS circuits.

Mindaugas Drazdziulis, Per Larsson-Edefors

Proceedings of the ESSCIRC 2003, 2003

Full-custom vs. standard-cell design flow: an adder case study.

Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation.

Daniel Eckerbert, Per Larsson-Edefors

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.

Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors

Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

2001

A regular parallel multiplier which utilizes multiple carry-propagate adders.

Henrik Eriksson, Per Larsson-Edefors, William P. Marnane

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.

Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Cycle-true leakage current modeling for CMOS gates.

Daniel Eckerbert, Per Larsson-Edefors

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

VLSI implementation of CRC-32 for 10 Gigabit Ethernet.

Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Interconnect-Driven Short-Circuit Power Modeling.

Daniel Eckerbert, Per Larsson-Edefors

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Impact of Voltage Scaling on Glitch Power Consumption.

Henrik Eriksson, Per Larsson-Edefors

Proceedings of the Integrated Circuit Design, 2000

An interconnect-driven design of a DFT processor.

Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

GLMC: interconnect length estimation by growth-limited multifold clustering.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A leakage-tolerant multi-phase keeper for wide domino circuits.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.

Atila Alvandpour, Per Larsson-Edefors, Christer Svensson

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A Miniature Serial-Data SIMD Architecture.

Per Larsson-Edefors

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996

Technology mapping onto very-high-speed standard CMOS hardware.

Per Larsson-Edefors

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier.

Per Larsson-Edefors

IEEE J. Solid State Circuits, 1996