Per Gunnar Kjeldsberg
Orcid: 0000-0001-9107-116X
According to our database1,
Per Gunnar Kjeldsberg
authored at least 43 papers
between 2000 and 2023.
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Bibliography
2023
Lens Flare Attenuation Accelerator Design with Deep Learning and High-Level Synthesis.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
2022
Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements.
IEEE Access, 2022
2021
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode.
J. Signal Process. Syst., 2021
2019
Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
2018
Algorithm/Architecture Co-optimisation Technique for Automatic Data Reduction of Wireless Read-Out in High-Density Electrode Arrays.
ACM Trans. Embed. Comput. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios.
Microprocess. Microsystems, 2018
2017
Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures.
Proceedings of the International Conference for High Performance Computing, 2017
READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures.
ACM Trans. Embed. Comput. Syst., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Dynamic Hardware Management of the H264/AVC Encoder Control Structure Using a Framework for System Scenarios.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
System scenario framework evaluation on EFM32 using the H264/AVC encoder control structure.
Proceedings of the European Conference on Circuit Theory and Design, 2015
Run-Time Exploitation of Application Dynamism for Energy-Efficient Exascale Computing (READEX).
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015
2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios.
Des. Autom. Embed. Syst., 2013
2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Performance and Energy Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
2009
Proceedings of the Embedded Computer Systems: Architectures, 2009
2008
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
J. Signal Process. Syst., 2008
Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
J. Signal Process. Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Power optimization of weighted bit-product summation tree for elementary function generator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
On the Impact of Fixed Point DSP Implementation on Required Channel Estimator Complexity in Communication Receivers.
Proceedings of the 4th IEEE International Symposium on Wireless Communication Systems, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Polyhedral space generation and memory estimation from interface and memory models of real-time video systems.
J. Syst. Softw., 2006
J. Embed. Comput., 2006
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2004
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
2002
Kluwer, ISBN: 978-0-7923-7689-7, 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.
Proceedings of the 38th Design Automation Conference, 2001
2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Storage requirement estimation for data intensive applications with partially fixed execution ordering.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000