Peng Ouyang
Orcid: 0000-0001-6598-3472
According to our database1,
Peng Ouyang
authored at least 66 papers
between 2010 and 2024.
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Bibliography
2024
Achieving popularity to attract more patients via free knowledge sharing in the online health community.
Aslib J. Inf. Manag., 2024
Automatic Tape-Application Equipment for Lithium-Ion Batteries: Dynamic Performance Simulation and Optimization Design.
Proceedings of the 6th International Conference on Internet of Things, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Proceedings of the 16th ACM International Conference on Systems and Storage, 2023
2022
Internet Res., 2022
Patients need emotional support: Managing physician disclosure information to attract more patients.
Int. J. Medical Informatics, 2022
The impact of gamification on the patient's engagement in the online health community.
Aslib J. Inf. Manag., 2022
2021
IEEE Trans. Instrum. Meas., 2021
GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant Environments.
Proceedings of the IEEE Automatic Speech Recognition and Understanding Workshop, 2021
2020
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.
CCF Trans. High Perform. Comput., 2020
Proceedings of the 21st Annual Conference of the International Speech Communication Association, 2020
Proceedings of the 21st Annual Conference of the International Speech Communication Association, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the 5th International Conference on Automation, 2020
2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019
IEEE Trans. Circuits Syst. Video Technol., 2019
An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width.
IEEE J. Solid State Circuits, 2019
J. Medical Syst., 2019
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the IEEE Automatic Speech Recognition and Understanding Workshop, 2019
2018
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
IEEE J. Solid State Circuits, 2018
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation.
IEEE Syst. J., 2017
Proceedings of the Symposium on Applied Computing, 2017
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
High-performance video content recognition with long-term recurrent convolutional network for FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A fast face detection architecture for auto-focus in smart-phones and digital cameras.
Sci. China Inf. Sci., 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature.
Sensors, 2015
Proceedings of the 2015 IEEE Winter Conference on Applications of Computer Vision, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps.
Sensors, 2014
A fast and robust traffic sign recognition method using ring of RIBP histograms based feature.
Proceedings of the 2014 IEEE International Conference on Robotics and Biomimetics, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 22nd International Conference on Pattern Recognition, 2014
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Sensors, 2013
Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010