Peng Liu

According to our database, Peng Liu authored at least 34 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices.

Yongqi Xu, Yujian Lee, Gao Yi, Bosheng Liu, Yucong Chen, Peng Liu, Jigang Wu, Xiaoming Chen, Yinhe Han

CoRR, 2024

A Complementary Resistive Switch-Based Balanced Ternary Logic.

Zhijian Peng, Peng Liu, Lian Yao, Zhiqiang You, Bosheng Liu, Yang Yi, Jigang Wu

Proceedings of the IEEE International Test Conference in Asia, 2024

Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs.

Yi Chen, Bosheng Liu, Yongqi Xu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs.

Bosheng Liu, Zhuoshen Jiang, Yalan Wu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han

IEEE Trans. Parallel Distributed Syst., December, 2023

Double-Layered Dual-Syndrome Trellis Codes Utilizing Channel Knowledge for Robust Steganography.

Qingxiao Guan, Peng Liu, Weiming Zhang, Wei Lu, Xinpeng Zhang

IEEE Trans. Inf. Forensics Secur., 2023

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach.

Bosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen, Peng Liu, Yinhe Han

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit.

Zhen Wang, Guofa Zhang, Peng Liu, Jing Ye, Jianhui Jiang

IEEE Trans. Very Large Scale Integr. Syst., 2022

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture.

Weizheng Wang, Xiangqi Wang, Jin Wang, Neal N. Xiong, Shuo Cai, Peng Liu

IEEE Trans. Syst. Man Cybern. Syst., 2022

Search-Free Inference Acceleration for Sparse Convolutional Neural Networks.

Bosheng Liu, Xiaoming Chen, Yinhe Han, Jigang Wu, Liang Chang, Peng Liu, Haobo Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Reconfiguration algorithms for synchronous communication on switch based degradable arrays.

Yalan Wu, Jigang Wu, Peng Liu, Yinhe Han, Thambipillai Srikanthan

Parallel Comput., 2022

An improved reconfigurable logic in resistive random access memory.

Yi Zhao, Hui Chen, Peng Liu, Jigang Wu, Dongxiang Luo

Integr., 2022

Fast algorithms for restoring survivable spanning connection.

Jiale Huang, Lulu Zheng, Yalan Wu, Peng Liu, Jigang Wu

Comput. Electr. Eng., 2022

2021

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.

Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han

IEEE Trans. Emerg. Top. Comput., 2021

Integrating Two Logics Into One Crossbar Array for Logic Gate Design.

Lian Yao, Peng Liu, Jigang Wu, Yinhe Han, Yuehang Zhong, Zhiqiang You

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fault Modeling and Efficient Testing of Memristor-Based Memory.

Peng Liu, Zhiqiang You, Jigang Wu, Bosheng Liu, Yinhe Han, Krishnendu Chakrabarty

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM.

Bosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, Peng Liu

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.

Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li

J. Electron. Test., 2020

Restoring Survivable Spanning Tree: An Alternative Algorithm.

Lulu Zheng, Yalan Wu, Jiale Huang, Peng Liu, Jigang Wu

Proceedings of the Parallel Architectures, Algorithms and Programming, 2020

Jointly Learning Multiple Curvature Descriptor for 3D Palmprint Recognition.

Lunke Fei, Jianyang Qin, Peng Liu, Jie Wen, Chunwei Tian, Bob Zhang, Shuping Zhao

Proceedings of the 25th International Conference on Pattern Recognition, 2020

2019

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.

Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai

IEEE Access, 2019

2018

An efficient controlled LFSR hybrid BIST scheme.

Tieqiao Liu, Peng Liu, Yi Liu

IEICE Electron. Express, 2018

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.

Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

A Novel Linguistic Steganography Based on Synonym Run-Length Encoding.

Lingyun Xiang, Xinhui Wang, Chunfang Yang, Peng Liu

IEICE Trans. Inf. Syst., 2017

A direct AC-DC converter integrated with SSHI circuit for piezoelectric energy harvesting.

Liao Wu, Chenrui Guo, Peng Liu, Wei Wang

IEICE Electron. Express, 2017

A novel test data compression approach based on bit reversion.

Shuo Cai, Yinbo Zhou, Peng Liu, Fei Yu, Wei Wang

IEICE Electron. Express, 2017

Reliability evaluation of logic circuits based on transient faults propagation metrics.

Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang

IEICE Electron. Express, 2017

2016

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.

Liao Wu, Jishun Kuang, Zhiqiang You, Peng Liu, Shuo Cai

IEICE Electron. Express, 2016

2015

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.

Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Weizheng Wang

IEICE Electron. Express, 2015

2013

Hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices.

Peng Liu, Jigang Wu, Yongji Wang

Math. Comput. Model., 2013

Low power logic BIST with high test effectiveness.

Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang

IEICE Electron. Express, 2013

2012

A scan disabling-based BAST scheme for test cost and test power reduction.

Zhiqiang You, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin

IEICE Electron. Express, 2012

Switching activity reduction for scan-based BIST using weighted scan input data.

Weizheng Wang, Jishun Kuang, Peng Liu, Xin Peng, Zhiqiang You

IEICE Electron. Express, 2012

Integrated Heuristic for Hardware/Software Co-design on Reconfigurable Devices.

Peng Liu, Jigang Wu, Yongji Wang

Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

2011

A scan disabling-based BAST scheme for test cost reduction.

Zhiqiang You, Weizheng Wang, Zhiping Dou, Peng Liu, Jishun Kuang

IEICE Electron. Express, 2011