Peng Liu

Orcid: 0000-0002-2329-502X

Affiliations:
  • Guangdong University of Technology, School of Computers, Guangzhou, China
  • Hunan University, College of Information Science and Engineering, Changsha, China (PhD 2017)


According to our database1, Peng Liu authored at least 35 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks.
IEEE Internet Things J., December, 2024

BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices.
CoRR, 2024

A Complementary Resistive Switch-Based Balanced Ternary Logic.
Proceedings of the IEEE International Test Conference in Asia, 2024

Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs.
IEEE Trans. Parallel Distributed Syst., December, 2023

Double-Layered Dual-Syndrome Trellis Codes Utilizing Channel Knowledge for Robust Steganography.
IEEE Trans. Inf. Forensics Secur., 2023

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture.
IEEE Trans. Syst. Man Cybern. Syst., 2022

Search-Free Inference Acceleration for Sparse Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Reconfiguration algorithms for synchronous communication on switch based degradable arrays.
Parallel Comput., 2022

An improved reconfigurable logic in resistive random access memory.
Integr., 2022

Fast algorithms for restoring survivable spanning connection.
Comput. Electr. Eng., 2022

2021
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.
IEEE Trans. Emerg. Top. Comput., 2021

Integrating Two Logics Into One Crossbar Array for Logic Gate Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fault Modeling and Efficient Testing of Memristor-Based Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.
J. Electron. Test., 2020

Restoring Survivable Spanning Tree: An Alternative Algorithm.
Proceedings of the Parallel Architectures, Algorithms and Programming, 2020

Jointly Learning Multiple Curvature Descriptor for 3D Palmprint Recognition.
Proceedings of the 25th International Conference on Pattern Recognition, 2020

2019
A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.
IEEE Access, 2019

2018
An efficient controlled LFSR hybrid BIST scheme.
IEICE Electron. Express, 2018

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
A Novel Linguistic Steganography Based on Synonym Run-Length Encoding.
IEICE Trans. Inf. Syst., 2017

A direct AC-DC converter integrated with SSHI circuit for piezoelectric energy harvesting.
IEICE Electron. Express, 2017

A novel test data compression approach based on bit reversion.
IEICE Electron. Express, 2017

Reliability evaluation of logic circuits based on transient faults propagation metrics.
IEICE Electron. Express, 2017

2016
A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.
IEICE Electron. Express, 2016

2015
Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.
IEICE Electron. Express, 2015

2013
Hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices.
Math. Comput. Model., 2013

Low power logic BIST with high test effectiveness.
IEICE Electron. Express, 2013

2012
A scan disabling-based BAST scheme for test cost and test power reduction.
IEICE Electron. Express, 2012

Switching activity reduction for scan-based BIST using weighted scan input data.
IEICE Electron. Express, 2012

Integrated Heuristic for Hardware/Software Co-design on Reconfigurable Devices.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

2011
A scan disabling-based BAST scheme for test cost reduction.
IEICE Electron. Express, 2011


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