Peng Liu
Orcid: 0000-0001-9107-6673Affiliations:
- Zhejiang University, Department of Information Science and Electronic Engineering, Hangzhou, China
According to our database1,
Peng Liu
authored at least 57 papers
between 2001 and 2023.
Collaborative distances:
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Bibliography
2023
RUPA: A High Performance, Energy Efficient Accelerator for Rule-Based Password Generation in Heterogenous Password Recovery System.
IEEE Trans. Computers, April, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
On a Consistency Testing Model and Strategy for Revealing RISC Processor's Dark Instructions and Vulnerabilities.
IEEE Trans. Computers, 2022
IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions.
IET Inf. Secur., 2022
High-Performance Password Recovery Hardware Going From GPU to Hybrid CPU-FPGA Platform.
IEEE Consumer Electron. Mag., 2022
2021
A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation.
IEEE Access, 2021
Hardware Trojan Detection Method for Inspecting Integrated Circuits Based on Machine Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
2019
An Energy-Efficient Accelerator Based on Hybrid CPU-FPGA Devices for Password Recovery.
IEEE Trans. Computers, 2019
Ensemble-Learning-Based Hardware Trojans Detection Method by Detecting the Trigger Nets.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Access, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking.
IEEE Trans. Computers, 2016
Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads.
ACM Trans. Archit. Code Optim., 2016
Microelectron. J., 2016
Comput. Electr. Eng., 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016
2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
J. Comput. Sci. Technol., 2014
A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
An efficient protocol with synchronization accelerator for multi-processor embedded systems.
Parallel Comput., 2013
Parallel Comput., 2013
J. Comput. Sci. Technol., 2013
Proceedings of the Network and Parallel Computing - 10th IFIP International Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Comput. Electr. Eng., 2012
2011
On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks.
Microprocess. Microsystems, 2011
Int. J. High Perform. Syst. Archit., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011
An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System.
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints.
ACM Trans. Archit. Code Optim., 2010
Int. J. High Perform. Syst. Archit., 2010
Int. J. High Perform. Syst. Archit., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
2009
Comput. Electr. Eng., 2009
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009
2005
Proceedings of the Electronic Imaging: Image and Video Communications and Processing 2005, 2005
2004
IEEE Trans. Consumer Electron., 2004
2002
Hardware/software codesign for HDTV source decoder on system level.
Proceedings of the Visual Communications and Image Processing 2002, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Proceedings of the Security and Watermarking of Multimedia Contents III, 2001