Peng Huang

According to our database, Peng Huang authored at least 30 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators.

Lixia Han, Renjie Pan, Zheng Zhou, Hairuo Lu, Yiyang Chen, Haozhang Yang, Peng Huang, Guangyu Sun, Xiaoyan Liu, Jinfeng Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network.

Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Lifeng Liu, Linxiao Shen, Peng Huang, Xiaoyan Liu, Jinfeng Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators.

Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu, Jinfeng Kang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

A 3.3-Mbit/s true random number generator based on resistive random access memory.

Shiyue Song, Peng Huang, Wensheng Shen, Lifeng Liu, Jinfeng Kang

Sci. China Inf. Sci., November, 2023

An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash.

Haozhang Yang, Peng Huang, Runze Han, Xiaoyan Liu, Jinfeng Kang

Sci. China Inf. Sci., April, 2023

Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy.

Guihai Yu, Peng Huang, Runze Han, Lixia Han, Xiaoyan Liu, Jinfeng Kang

Sci. China Inf. Sci., February, 2023

A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization.

Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Xiaoyan Liu, Jinfeng Kang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Floating Gate Transistor-Based Accurate Digital In-Memory Computing for Deep Neural Networks.

Runze Han, Peng Huang, Yachen Xiang, Hong Hu, Sheng Lin, Peiyan Dong, Wensheng Shen, Yanzhi Wang, Xiaoyan Liu, Jinfeng Kang

Adv. Intell. Syst., December, 2022

Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory.

Lixia Han, Peng Huang, Yijiao Wang, Zheng Zhou, Yizhou Zhang, Xiaoyan Liu, Jinfeng Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

Flash Memory Array for Efficient Implementation of Deep Neural Networks.

Runze Han, Yachen Xiang, Peng Huang, Yihao Shan, Xiaoyan Liu, Jinfeng Kang

Adv. Intell. Syst., 2021

Novel Weight Mapping Method for Reliable NVM based Neural Network.

Lixia Han, Yachen Xiang, Peng Huang, Guihai Yu, Runze Han, Xiaoyan Liu, Jinfeng Kang

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2019

A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency.

Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhen Dong, Zhiqiang Su, Yongbo Liu, Lu Liu, Xiaoyan Liu, Jinfeng Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning.

Yuning Jiang, Peng Huang, Zheng Zhou, Jinfeng Kang

Sci. China Inf. Sci., 2019

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing.

Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang

Sci. China Inf. Sci., 2019

Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation.

Yachen Xiang, Peng Huang, Zheng Zhou, Runze Han, Yuning Jiang, Q. M. Shu, Zhiqiang Su, Yongbo Liu, Xiaoyan Liu, Jinfeng Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network.

Min Zhang, Peng Huang, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang

Proceedings of the 13th IEEE International Conference on ASIC, 2019

3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model.

Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Flash-based Computing in-Memory Scheme for IOT.

Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.

Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition.

Yuning Jiang, Peng Huang, Dongbin Zhu, Zheng Zhou, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient.

Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhekang Dong, Zhiqiang Su, Yongbo Liu, L. Liu, Xiaoyan Liu, Jinfeng Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

PBTI evaluation of In0.65Ga0.35As/In0.53Ga0.47As nanowire FETs with Al2O3 and LaAlO3 gate dielectrics.

Yun Li, K. L. Wang, Shaoyan Di, Peng Huang, Gang Du, Xiao-Yan Liu

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016

Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays.

Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong

CoRR, 2016

Physical understanding and optimization of resistive switching characteristics in oxide-RRAM.

Jinfeng Kang, Peng Huang, Zhe Chen, Yudi Zhao, Chen Liu, Runze Han, Lifeng Liu, Xiaoyan Liu, Yangyuan Wang, Bin Gao

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

RRAM based synaptic devices for neuromorphic visual systems.

Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.

Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Modeling and design optimization of ReRAM.

Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Design guidelines for 3D RRAM cross-point architecture.

Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.

Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Parameters extraction on HfOX based RRAM.

Peng Huang, Bing Chen, Haitong Li, Zhe Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang

Proceedings of the 44th European Solid State Device Research Conference, 2014