Peng Gu

Orcid: 0000-0002-2663-4568

According to our database1, Peng Gu authored at least 69 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
K/Ka-Band Hybrid-Packaged Four-Element Four-Beam Phased-Array Transmitter and Receiver Front-Ends With Optimized Beamforming Passive Networks.
IEEE J. Solid State Circuits, October, 2024

A novel adaptive maximum correntropy cubature Kalman filter based on multiple fading factors.
Trans. Inst. Meas. Control, 2024

2023
DNN-Based Fractional Doppler Channel Estimation for OTFS Modulation.
IEEE Trans. Veh. Technol., November, 2023

A Wideband Low-Loss CMOS Attenuator With dB-Linear Gain Tuning for W-Band Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

A DC-87.8-GHz Switched-Type Attenuator With Switched Capacitor Branch in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing.
ACM Trans. Archit. Code Optim., September, 2023

Security control scheme for cyber-physical system with a complex network in physical layer against false data injection attacks.
Appl. Math. Comput., June, 2023

Robust adaptive multi-target tracking with unknown heavy-tailed noise.
IET Signal Process., February, 2023

A 2.5m Long-Range IPT System Based on Domino Cylindrical Solenoid Coupler Compensated Respectively in Layers.
IEEE Trans. Ind. Electron., 2023

No calibration required two-step double-data-rate counter for low-power SS ADC in CMOS image sensors.
Microelectron. J., 2023

K/Ka-Band 4-Element 4-Beam Hybrid Phased-Array Transmitter and Receiver Front-Ends with Compact Layout Floor-Plans and Fault-Tolerant Digital Circuits.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
Analysis and Design of Cubic Magnetic Coupler for High Distance-to-Diameter Ratio IPT Systems.
IEEE Trans. Ind. Electron., 2022

Analysis, Design, and Optimization of the IPT System With LC Filter Rectifier Featuring High Efficiency.
IEEE Trans. Ind. Electron., 2022

A 24-29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio.
IEEE J. Solid State Circuits, 2022

MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures.
IEEE Comput. Archit. Lett., 2022

Channel Estimation of mmWave Massive MIMO System Based on Manifold Learning.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2021
Architecture Supports and Optimizations for Memory-Centric Processing System
PhD thesis, 2021

Corrections to "Millimeter-Wave Integrated Phased Arrays" [early access, Jul 12, 21 doi: 10.1109/TCSI.2021.3093093].
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Millimeter-Wave Integrated Phased Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analysis and Design of a CMOS Bidirectional Passive Vector-Modulated Phase Shifter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Object Detection Combining CNN and Adaptive Color Prior Features.
Sensors, 2021

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.
CoRR, 2021

A Ka-Band Balanced Four-Beam Phased-Array Receiver With Symmetrical Beam-Distribution Network in 65-nm CMOS.
IEEE Access, 2021

A Ka-Band CMOS Switched-Type Phase Shifter with Low Gain Error.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Research on Recommender System Based on Curiosity Guided Identity Modification.
Proceedings of the AIAM 2021: 3rd International Conference on Artificial Intelligence and Advanced Manufacture, Manchester, United Kingdom, October 23, 2021

2020
A DC-50 GHz CMOS Switched-Type Attenuator With Capacitive Compensation Technique.
IEEE Trans. Circuits Syst., 2020

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.
ACM Trans. Archit. Code Optim., 2020

NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices.
IEEE Comput. Archit. Lett., 2020

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.
IEEE Comput. Archit. Lett., 2019

Design and Implementation of Software Test Laboratory Based on Cloud Platform.
Proceedings of the 19th IEEE International Conference on Software Quality, 2019

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

5G Millimeter-Wave Phased-Array Transceiver: System Considerations and Circuit Implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Group Recommendation Approach Based on Neural Network Collaborative Filtering.
Proceedings of the 35th IEEE International Conference on Data Engineering Workshops, 2019

A DC-43.5 GHz CMOS Switched-Type Attenuator with Capacitive Compensation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Peer-to-peer Detection of DoS Attacks on City-Scale IoT Mesh Networks.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Application of FBG Sensing Technology in Stability Analysis of Geogrid-Reinforced Slope.
Sensors, 2017

Many-objective harmony search for integrated order planning in steelmaking-continuous casting-hot rolling production of multi-plants.
Int. J. Prod. Res., 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol., 2016

Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing.
IEEE Des. Test, 2016

Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Thermal-aware 3D design for side-channel information leakage.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
RRAM-Based Analog Approximate Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2011
A New Placement-Ideal Layout for Multiway Replication Storage System.
IEEE Trans. Computers, 2011

2010
A Novel Weighted-Graph-Based Grouping Algorithm for Metadata Prefetching.
IEEE Trans. Computers, 2010

2009
A New Hierarchical Data Cache Architecture for iSCSI Storage Server.
IEEE Trans. Computers, 2009

An advertisement-based peer-to-peer search algorithm.
J. Parallel Distributed Comput., 2009

2008
Metadata Management for Distributed Multimedia Storage System.
Proceedings of The International Symposium on Electronic Commerce and Security, 2008

Shifted declustering: a placement-ideal layout scheme for multi-way replication storage architecture.
Proceedings of the 22nd Annual International Conference on Supercomputing, 2008

Bridging the Gap Between Parallel File Systems and Local File Systems: A Case Study with PVFS.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007
ASAP: An Advertisement-based Search Algorithm for Unstructured Peer-to-peer Systems.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007

2006
Nexus: A Novel Weighted-Graph-Based Prefetching Algorithm for Metadata Servers in Petabyte-Scale Storage Systems.
Proceedings of the Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 2006

2004
RAMS: a RDMA-enabled I/O cache architecture for clustered network servers.
Proceedings of the International Workshop on Storage Network Architecture and Parallel I/Os, 2004


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