Peng Feng

Affiliations:
  • Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China
  • University of Chinese Academy of Sciences, Center of Materials Science and Optoelectronics Engineering, Beijing, China


According to our database1, Peng Feng authored at least 22 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging.
Sensors, July, 2024

A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision.
IEEE J. Solid State Circuits, June, 2024

2023
A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022
A 1000 fps Spiking Neural Network Tracking Algorithm for On-Chip Processing of Dynamic Vision Sensor Data.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Pixel Design of Ultra-high Speed CMOS Image Sensor.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
TBC-Net: A real-time detector for infrared small target detection using semantic constraint.
CoRR, 2020

A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper).
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application.
IET Circuits Devices Syst., 2019

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors.
IEICE Electron. Express, 2019

2018
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.
IEICE Electron. Express, 2017

A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications.
IEEE Trans. Biomed. Circuits Syst., 2011

2010
A novel RFID tag chip with temperature sensor in standard CMOS process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An ultra low power non-volatile memory in standard CMOS process for passive RFID tags.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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