Pen-Jui Peng
Orcid: 0000-0001-5736-5746
According to our database1,
Pen-Jui Peng
authored at least 15 papers
between 2013 and 2024.
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Bibliography
2024
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS.
IEEE J. Solid State Circuits, 2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
2021
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021
A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013