Pen-Chung Yew
Orcid: 0000-0001-9653-8777Affiliations:
- University of Minnesota, USA
According to our database1,
Pen-Chung Yew
authored at least 210 papers
between 1981 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1998, "For contributions to the design of high-performance shared-memory multiprocessors and their parallelizing compilers.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
ACM Trans. Archit. Code Optim., March, 2024
A System-Level Dynamic Binary Translator Using Automatically-Learned Translation Rules.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024
2023
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Parallel Distributed Syst., June, 2023
SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution Attacks.
IEEE Trans. Dependable Secur. Comput., 2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
2022
IEEE Trans. Dependable Secur. Comput., 2022
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022
2021
Ascetic: Enhancing Cross-Iterations Data Efficiency in Out-of-Memory Graph Processing on GPUs.
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
2020
Proceedings of the Middleware '20: 21st International Middleware Conference, 2020
More with Less - Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020
2019
A formally verified transformation to unify multiple nested clocks for a Lustre-like language.
Sci. China Inf. Sci., 2019
SafeHidden: An Efficient and Secure Information Hiding Technique Using Re-randomization.
Proceedings of the 28th USENIX Security Symposium, 2019
Unleashing the Power of Learning: An Enhanced Learning-Based Approach for Dynamic Binary Translation.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019
2018
RARE: An Efficient Static Fault Detection Framework for Definition-Use Faults in Large Programs.
IEEE Access, 2018
Proceedings of the 14th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2018
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-Core.
IEEE Trans. Parallel Distributed Syst., 2017
IEEE Trans. Parallel Distributed Syst., 2017
Proceedings of the 15th Annual International Conference on Mobile Systems, 2017
A formally verified sequentializer for lustre-like concurrent synchronous data-flow programs.
Proceedings of the 39th International Conference on Software Engineering, 2017
2016
Proceedings of the 2016 USENIX Annual Technical Conference, 2016
Proceedings of the 2016 International Conference on Supercomputing, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
WiseThrottling: a new asynchronous task scheduler for mitigating I/O bottleneck in large-scale datacenter servers.
J. Supercomput., 2015
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor.
ACM Trans. Archit. Code Optim., 2015
Adaptive granularity and coordinated management for timely prefetching in multi-core systems.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2015
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking.
ACM Trans. Archit. Code Optim., 2014
Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms.
J. Comput. Sci. Technol., 2014
DBILL: an efficient and retargetable dynamic binary instrumentation framework using llvm backend.
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014
Proceedings of the ACM/IEEE International Conference on Automated Software Engineering, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 2014 International Conference on Supercomputing, 2014
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution.
IEEE Trans. Computers, 2013
Cross-layer dynamic prefetching allocation strategies for high-performance multicores.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Improving dynamic binary optimization through early-exit guided code region formation.
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013
Proceedings of the 2013 IEEE 6th International Conference on Service-Oriented Computing and Applications, 2013
Proceedings of the Research in Adaptive and Convergent Systems, 2013
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
ACM Trans. Archit. Code Optim., 2012
A Study of Performance Portability Using Piecewise-Parabolic Method (PPM) Gas Dynamics Applications.
Proceedings of the International Conference on Computational Science, 2012
J. Comput. Sci. Technol., 2012
Code Transformations for Enhancing the Performance of speculatively Parallel Threads.
J. Circuits Syst. Comput., 2012
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
IEEE Trans. Software Eng., 2011
Sci. China Inf. Sci., 2011
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends.
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the Programming Languages and Systems - 9th Asian Symposium, 2011
2010
Boosting the performance of computational fluid dynamics codes for interactive supercomputing.
Proceedings of the International Conference on Computational Science, 2010
Proceedings of the CGO 2010, 2010
Proceedings of the CGO 2010, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009
Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs.
Proceedings of the CGO 2009, 2009
2008
Compiler optimizations for parallelizing general-purpose applications under thread-level speculation.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.
Proceedings of the 26th International Conference on Computer Design, 2008
2007
IEEE Comput. Archit. Lett., 2007
Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization.
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007
Proceedings of the 29th International Conference on Software Engineering (ICSE 2007), 2007
COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007
Proceedings of the Advances in Computer Systems Architecture, 2007
Proceedings of the Advances in Computer Systems Architecture, 2007
Entropy-Based Profile Characterization and Classification for Automatic Profile Management.
Proceedings of the Advances in Computer Systems Architecture, 2007
2006
IEEE Trans. Parallel Distributed Syst., 2006
ACM Trans. Archit. Code Optim., 2006
Proceedings of the 2nd International Conference on Virtual Execution Environments, 2006
Proceedings of the Languages and Compilers for Parallel Computing, 2006
Proceedings of the High Performance Computing, 2006
2005
IEICE Trans. Inf. Syst., 2005
Proceedings of the Languages and Compilers for Parallel Computing, 2005
Proceedings of the Parallel and Distributed Processing and Applications, 2005
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005
A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005
2004
ACM Trans. Archit. Code Optim., 2004
J. Instr. Level Parallelism, 2004
Proceedings of the Compiler Construction, 13th International Conference, 2004
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
A Compiler Framework for Recovery Code Generation in General Speculative Optimizations.
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004
2003
Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, 2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
Is There Exploitable Thread-Level Parallelism in General-Purpose Application Programs?
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003
2002
IEEE Trans. Computers, 2002
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002
Proceedings of the International Symposium on Parallel Architectures, 2002
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002
2001
On Table Bandwidth and Its Update Delay for Value Prediction on Wide-Issue ILP Processors.
IEEE Trans. Computers, 2001
IEEE Trans. Computers, 2001
J. Parallel Distributed Comput., 2001
2000
Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance.
IEEE Trans. Parallel Distributed Syst., 2000
Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study.
IEEE Trans. Parallel Distributed Syst., 2000
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000
1999
IEEE Trans. Parallel Distributed Syst., 1999
J. Syst. Archit., 1999
Int. J. Parallel Program., 1999
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999
Proceedings of the Languages and Compilers for Parallel Computing, 1999
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999
1998
J. Parallel Distributed Comput., 1998
Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading.
J. Inf. Sci. Eng., 1998
Proceedings of the Languages and Compilers for Parallel Computing, 1998
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998
High-Level Information - An Approach for Integrating Front-End and Back-End Compilers.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
1997
J. Parallel Distributed Comput., 1997
Proceedings of the Languages and Compilers for Parallel Computing, 1997
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997
1996
IEEE Trans. Parallel Distributed Syst., 1996
Integrating Fine-Grained Message Passing in Cache Coherent Shared Memory Multiprocessors.
J. Parallel Distributed Comput., 1996
Chief: A Simulation Environment for Studying Parallel Systems.
Int. J. Comput. Simul., 1996
IEEE Parallel Distributed Technol. Syst. Appl., 1996
Compiler Support for Maintaining Cache Coherence Using Data Prefetching (Extended Abstract).
Proceedings of the Languages and Compilers for Parallel Computing, 1996
Proceedings of the Languages and Compilers for Parallel Computing, 1996
Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996
Proceedings of IPPS '96, 1996
Proceedings of the 1996 International Conference on Parallel Processing Workshop, 1996
Proceedings of the 1996 International Conference on Parallel Processing, 1996
The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996
1995
J. Parallel Distributed Comput., 1995
Proceedings of the 27th conference on Winter simulation, 1995
Proceedings of the Ninth Workshop on Parallel and Distributed Simulation, 1995
Proceedings of the Languages and Compilers for Parallel Computing, 1995
1994
Proceedings of the Proceedings Supercomputing '94, 1994
Proceedings of the Proceedings Supercomputing '94, 1994
Proceedings of the Eighth Workshop on Parallel and Distributed Simulation, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
1993
IEEE Trans. Parallel Distributed Syst., 1993
Execution-driven tools for parallel simulation of parallel architectures and applications.
Proceedings of the Proceedings Supercomputing '93, 1993
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993
1992
ACM Trans. Comput. Syst., 1992
Proceedings of the 6th International Parallel Processing Symposium, 1992
A Scheme for Effective Execution of Irregular Doacross Loops.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
1991
J. Parallel Distributed Comput., 1991
Proceedings of the Proceedings Supercomputing '91, 1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Proceedings of the 5th international conference on Supercomputing, 1991
Proceedings of the 5th international conference on Supercomputing, 1991
Efficient Interprocessor Communication on Distributed Shared-Memory Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1991
The Organization of the Cedar System.
Proceedings of the International Conference on Parallel Processing, 1991
The Performance of Hierarchical Systems with Wiring Constraints.
Proceedings of the International Conference on Parallel Processing, 1991
Proceedings of the Proceedings 24th Annual Simulation Symposium (ANSS-24 1991), 1991
1990
IEEE Trans. Parallel Distributed Syst., 1990
IEEE Trans. Parallel Distributed Syst., 1990
IEEE Trans. Computers, 1990
J. Parallel Distributed Comput., 1990
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990
Proceedings of the 4th international conference on Supercomputing, 1990
Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors.
Proceedings of the 1990 International Conference on Parallel Processing, 1990
1989
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989
Proceedings of the 3rd international conference on Supercomputing, 1989
An Empirical Study on Array Subscripts and Data Dependencies.
Proceedings of the International Conference on Parallel Processing, 1989
Proceedings of the 13th Annual International Computer Software and Applications Conference, 1989
1988
IEEE Trans. Computers, 1988
Proceedings of the ACM/SIGPLAN PPEALS 1988, 1988
Proceedings of the 2nd international conference on Supercomputing, 1988
Interprocedural Analysis for Parallel Programs.
Proceedings of the International Conference on Parallel Processing, 1988
1987
IEEE Trans. Software Eng., 1987
IEEE Trans. Computers, 1987
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987
: Data Prefetching In Shared Memory Multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1987
An Enhancement Scheme for Hypercube Interconnection Networks.
Proceedings of the International Conference on Parallel Processing, 1987
Deadlock Prevention in Processor Self-Scheduling for Parallel Nested Loops.
Proceedings of the International Conference on Parallel Processing, 1987
1986
Distributing Hot-Spot Addressing in Large Scale Multiprocessor.
Proceedings of the International Conference on Parallel Processing, 1986
Processor Self-Scheduling for Multiple-Nested Parallel Loops.
Proceedings of the International Conference on Parallel Processing, 1986
1985
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985
The Performance of a Fault-Tolerant Multistage Interconnection Network.
Proceedings of the International Conference on Parallel Processing, 1985
1984
A Synchronization Scheme and Its Applications for Large Multiprocessor Systems.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984
1982
A fault tolerant interconnection network using error correcting codes.
Proceedings of the International Conference on Parallel Processing, 1982
Performance of packet switching in buffered single-stage shuffle-exchange networks.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982
1981
PhD thesis, 1981
IEEE Trans. Computers, 1981