Peizhou Gan
According to our database1,
Peizhou Gan
authored at least 6 papers
between 2019 and 2024.
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2024
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Bibliography
2024
Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation (Extended Version).
IACR Cryptol. ePrint Arch., 2024
Classic McEliece Hardware Implementation with Enhanced Side-Channel and Fault Resistance.
IACR Cryptol. ePrint Arch., 2024
Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2021
An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2019
A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Highly-Reliable and Energy-Efficient Physical Unclonable Function Based on 4T All-MOSFET Subthreshold Voltage Reference.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019