Peiyuan Wan
Orcid: 0000-0003-4875-6432
According to our database1,
Peiyuan Wan
authored at least 29 papers
between 2010 and 2024.
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Bibliography
2024
A fast-response RBCOT buck converter with second-order differential and integrator compensation based on FVF.
Microelectron. J., 2024
A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Design of analog front-end integrated circuit of tactile sensor for human-machine interface.
Integr., November, 2023
A 4-Channel Neural Stimulation IC Design With Charge Balancing and Multiple Current Output Modes.
IEEE Trans. Biomed. Circuits Syst., October, 2023
A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application.
IEEE Trans. Biomed. Circuits Syst., October, 2023
A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration.
IEICE Electron. Express, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
IEICE Electron. Express, 2022
Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique.
IEICE Electron. Express, 2022
A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine Interface.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 4-Channel Neural Stimulation IC Design with Charge Balancing and Exponential Current Output.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 4x folding voltage-to-time converter with adjustable conversion gain and offset for time-based ADC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
IEICE Trans. Electron., 2019
2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
J. Circuits Syst. Comput., 2013
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A High Linearity 6<sup>th</sup>-order active R-MOSFET-C band-pass filter for power-line communication.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010