Peisu Xia

According to our database¹, Peisu Xia authored at least 4 papers between 1995 and 1998.

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1998

Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 1998

1997

Out-of-order execution in sequentially consistent shared-memory systems.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 1997

1996

Event Ordering Condition for Correct Executions in Shared-Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

1995

A maximum time difference pipelined arithmetic unit based on CMOS gate array.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 1995