Peishan Tu

Orcid: 0000-0002-1727-8119

According to our database1, Peishan Tu authored at least 10 papers between 2015 and 2020.

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Bibliography

2020
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
FIT: Fill Insertion Considering Timing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A two-step search engine for large scale boolean matching under NP3 equivalence.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Timing driven routing tree construction.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Fence-aware detailed-routability driven placement.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
An Effective Chemical Mechanical Polishing Fill Insertion Approach.
ACM Trans. Design Autom. Electr. Syst., 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
An Effective Chemical Mechanical Polishing Filling Approach.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015


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