Pei-Yuan Chou
Orcid: 0000-0002-2414-9606
According to our database1,
Pei-Yuan Chou
authored at least 8 papers
between 2014 and 2024.
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Bibliography
2024
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
2019
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.
IEEE J. Solid State Circuits, 2015
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm<sup>2</sup> all-digital delay-locked loop in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014