Pei-Yuan Chiang
According to our database1,
Pei-Yuan Chiang
authored at least 8 papers
between 2013 and 2022.
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Bibliography
2022
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.
IEEE J. Solid State Circuits, 2021
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 28-nm 75-fs<sub>rms</sub> Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.
IEEE J. Solid State Circuits, 2019
2014
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013