Pedro P. Carballo

According to our database, Pedro P. Carballo authored at least 11 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2023

MPSoC FPGA Implementation of Algorithms of Machine Learning for Clinical Applications Using High-Level Design Methodology.

Mario Guanche-Hernández, Raquel León, Pedro P. Carballo

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations.

Gabriel Santana Quintana, Pedro P. Carballo, Carlos Betancor

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics.

Selenia María Medina Hernández, Pedro P. Carballo, Pedro Hernández-Fernández, David S. Miranda Guillén, Sergio González

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2019

Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs.

Raquel León, Adrián Domínguez, Pedro P. Carballo, Antonio Núñez

Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2017

Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm.

Adrián Domínguez, Pedro P. Carballo, Antonio Núñez

Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

2013

Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology.

Pedro P. Carballo, Omar Espino, Romén Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Núñez

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2006

VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems.

Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2004

CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip.

Víctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Pedro P. Carballo, Wido Kruijtzer

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

1993

Integer and control units for a GaAs 32-bit RISC processor.

Pedro P. Carballo, Roberto Sarmiento, Antonio Núñez

Microprocess. Microprogramming, 1993

1991

Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation.

K. Eshraghian, Roberto Sarmiento, Pedro P. Carballo, Antonio Núñez

Microprocessing and Microprogramming, 1991

1989

Some results in GaAs processor design using LSI integrated circuits.

Antonio Núñez, Roberto Sarmiento, Pedro P. Carballo

Microprocess. Microprogramming, 1989