Pedro Julián

Orcid: 0000-0002-6308-4497

Affiliations:
  • National Scientific and Technical Research Council (CONICET), Buenos Aires, Argentina
  • Universidad Nacional del Sur, Bahía Blanca, Argentina


According to our database1, Pedro Julián authored at least 57 papers between 1999 and 2024.

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Bibliography

2024
Soil analysis with machine-learning-based processing of stepped-frequency GPR field measurements: Preliminary study.
CoRR, 2024

2023
System on Chip Testbed for Deep Neuromorphic Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Architecture Analysis for Symmetric Simplicial Deep Neural Networks on Chip.
Proceedings of the 57th Annual Conference on Information Sciences and Systems, 2023

2022
Embedded Processing Pipeline Exploration For Neuromorphic Event Based Perceptual Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Morphological, Object Detection Framework for Embedded, Event-based Sensing.
Proceedings of the 8th International Conference on Event-Based Control, 2022

2021
Simplicial computation: A methodology to compute vector-vector multiplications with reduced complexity.
Int. J. Circuit Theory Appl., 2021

Symmetric Simplicial Neural Networks.
Proceedings of the 55th Annual Conference on Information Sciences and Systems, 2021

Event-based hand shadow recognition with varied light intensity and background subtraction.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
7 TOPS/W Cellular Neural Network Processor Core for Intelligent Internet-of-Things.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A Simplicial Piecewise Linear Approach for Efficient Hardware Realization of Neural Networks : (Invited Presentation).
Proceedings of the 53rd Annual Conference on Information Sciences and Systems, 2019

2018
Neuromorphic Cellular Neural Network Processor for Intelligent Internet-of-Things.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Guest Editorial Special Section on the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016).
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Bio-inspired system architecture for energy efficient, BIGDATA computing with application to wide area motion imagery.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

A true Random Number Generator using RTN noise and a sigma delta converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Analysis of time delay difference due to parametric mismatch in matched filter channels.
Int. J. Circuit Theory Appl., 2015

Step down DC/DC converter for micro-power medical applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Analysis of source separation algorithms in industrial acoustic environments.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Design of a vanishing point algorithm for custom ASIC.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

2014
Methodology and Measurement Setup for Analog-to-Digital Converter Postcompensation.
IEEE Trans. Instrum. Meas., 2014

SCDVP: A Simplicial CNN Digital Visual Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeam.
Proceedings of the 14th Latin American Test Workshop, 2013

A dual core low power microcontroller with openMSP430 architecture for high reliability lockstep applications using a 180 nm high voltage technology node.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2011
Application-Specific Processor for Piecewise Linear Functions Computation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Evaluation of Gunshot Detection Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
Carbon Nanotube Integration with a CMOS Process.
Sensors, 2010

Integrated circuit implementation of multi-dimensional piecewise-linear functions.
Digit. Signal Process., 2010

PWL cores for nonlinear array processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Radiation damage characterization of digital integrated circuits.
Proceedings of the 10th Latin American Test Workshop, 2009

2007
A comparison of low power architectures for digital delay measurement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Bounded state space particle filter for network sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Simplicial PWL Integrated Circuit Realization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A low-power correlation-derivative CMOS VLSI circuit for bearing estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

VLSI implementation of an energy-aware wake-up detector for an acoustic surveillance sensor network.
ACM Trans. Sens. Networks, 2006

A simplicial CNN visual processor in 3D SOI-CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Synthesis of multiport resistors with piecewise-linear characteristics: a mixed-signal architecture.
Int. J. Circuit Theory Appl., 2005

Hybrid sensor network and fusion algorithm for sound source localization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Field test results for low power bearing estimator sensor nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A scalable and programmable simplicial CNN digital pixel processor architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A comparative study of sound localization algorithms for energy aware sensor network nodes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A simplicial CNN architecture for on-chip image processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A wake-up detector for an acoustic surveillance sensor network: algorithm and VLSI implementation.
Proceedings of the Third International Symposium on Information Processing in Sensor Networks, 2004

2003
Exploiting piecewise linear features: multinested and simplicial cellular neural/nonlinear networks.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A comparison of algorithms for sound localization.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A low-power CMOS integrated circuit for bearing estimation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications.
IEEE Trans. Neural Networks, 2002

Replication Properties of Parity Cellular Automata.
Int. J. Bifurc. Chaos, 2002

A search algorithm for the design of multinested cellular neural networks.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Rtd-Based Cellular Neural Networks with Multiple steady States.
Int. J. Bifurc. Chaos, 2001

Towards the circuit implementation of the Hodgkin-Huxley neuron model: A PWL approach.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A piecewise-linear simplicial coupling cell for CNN gray-level image processing.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A robust and efficient universal CNN cell circuit using simplicial neuro-fuzzy inferences for fast image processing.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A model reduction procedure for high level canonical PWL functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Volterra kernels description using piecewise linear functions.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Orthonormal high level canonical PWL functions.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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