Pedro C. Diniz

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

Controlling a complete hardware synthesis toolchain with LARA aspects.

[BibT_eX]

[DOI]

Tiago Carvalho

Microprocess. Microsystems, 2013

Specifying Adaptations through a DSL with an Application to Mobile Robot Navigation.

[BibT_eX]

[DOI]

Proceedings of the 2nd Symposium on Languages, Applications and Technologies, 2013

The MATISSE MATLAB compiler.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Industrial Informatics, 2013

Robust graph traversal: Resiliency techniques for data intensive supercomputing.

[BibT_eX]

[DOI]

Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

A Case for Adaptive Redundancy for HPC Resilience.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Poster: Programming Model Extensions for Resilience in Extreme Scale Computing.

[BibT_eX]

[DOI]

Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Special session on "programming paradigms for reconfigurable multi-core embedded systems".

[BibT_eX]

[DOI]

Diana Göhringer

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Hardware/software specialization through aspects: The LARA approach.

[BibT_eX]

[DOI]

Fernando M. Gonçalves

Zlatko Petrov

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Resiliency-aware Scheduling for reconfigurable VLIW processors.

[BibT_eX]

[DOI]

Jeremy Abramson

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Resiliency-aware scheduling: Resource allocation for hardened computation on configurable devices.

[BibT_eX]

[DOI]

Jeremy Abramson

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A resiliency-aware scheduling approach for FPGA configuration: Preliminary results.

[BibT_eX]

[DOI]

Jeremy Abramson

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Specifying Compiler Strategies for FPGA-based Systems.

[BibT_eX]

[DOI]

Wayne Luk

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Programming Model Extensions for Resilience in Extreme Scale Computing.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

A programming model for resilience in extreme scale computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2012

Controlling Hardware Synthesis with Aspects.

[BibT_eX]

[DOI]

Tiago Carvalho

Zlatko Petrov

Wayne Luk

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.

[BibT_eX]

[DOI]

Sujit Bhattacharya

Wayne Luk

George A. Constantinides

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Experiments with the LARA aspect-oriented approach.

[BibT_eX]

[DOI]

Proceedings of the Companion Volume of the 11th International Conference on Aspect-oriented Software Development, 2012

LARA: an aspect-oriented programming language for embedded systems.

[BibT_eX]

[DOI]

Tiago Carvalho

Proceedings of the 11th International Conference on Aspect-oriented Software Development, 2012

2011

Domain-Specific Optimization of Signal Recognition Targeting FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

Data Reorganization and Prefetching of Pointer-Based Data Structures.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Introduction.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

A Domain-Specific Language for the Specification of Adaptable Context Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

2010

Preprocessing techniques for context recognition from accelerometer data.

[BibT_eX]

[DOI]

Pers. Ubiquitous Comput., 2010

Providing user context for mobile and social networking applications.

[BibT_eX]

[DOI]

Pervasive Mob. Comput., 2010

Compiling for reconfigurable computing: A survey.

[BibT_eX]

[DOI]

Markus Weinhardt

ACM Comput. Surv., 2010

High Performance Architectures and Compilers.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009

Introduction to the Special Issue ARC'08.

[BibT_eX]

[DOI]

Katherine Compton

Roger F. Woods

Christos-Savvas Bouganis

ACM Trans. Reconfigurable Technol. Syst., 2009

Guest Editorial.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2009

Mobile Context Provider for Social Networking.

[BibT_eX]

[DOI]

Proceedings of the On the Move to Meaningful Internet Systems: OTM 2009 Workshops, 2009

Context Inference for Mobile Applications in the UPCASE Project.

[BibT_eX]

[DOI]

Proceedings of the Mobile Wireless Middleware, 2009

Code Transformations for Embedded Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Proceedings of the Generative and Transformational Techniques in Software Engineering III, 2009

Computation reuse in domain-specific optimization of signal recognition.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Introduction.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008

A compiler approach to managing storage and memory bandwidth in configurable architectures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

The potential of computation reuse in high-level optimization of a signal recognition system.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Automatic Extraction of Process Control Flow from I/O Operations.

[BibT_eX]

[DOI]

Diogo R. Ferreira

Proceedings of the Business Process Management, 6th International Conference, 2008

2007

Exploiting parallelism in configurable architectures through custom array mapping.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2007

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops.

[BibT_eX]

[DOI]

Rui Rodrigues

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

An overview of the ECO project.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.

[BibT_eX]

[DOI]

Gokul Govindu

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures.

[BibT_eX]

[DOI]

Priyadarshini L. Malusare

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2005

Empirical Optimization for a Sparse Linear Solver: A Case Study.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2005

Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures.

[BibT_eX]

[DOI]

Heidi E. Ziegler

Proceedings of the Languages and Compilers for Parallel Computing, 2005

Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.

[BibT_eX]

[DOI]

K. R. Shesha Shayee

IEEE Trans. Computers, 2004

Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Modeling Loop Unrolling: Approaches and Open Issues.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Extending the Applicability of Scalar Replacement to Multiple Induction Variables.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for High Performance Computing, 2004

A Case Study Using Empirical Optimization for a Large, Engineering Application.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

2003

Eliminating synchronization bottlenecks using adaptive replication.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 2003

Increasing the Accuracy of Shape and Safety Analysis of Pointer-Based Codes.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2003

ECO: An Empirical-Based Compilation and Optimization System.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Compiler Approach to Performance Prediction Using Empirical-Based Modeling.

[BibT_eX]

[DOI]

Proceedings of the Computational Science - ICCS 2003, 2003

Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations.

[BibT_eX]

[DOI]

K. R. Shesha Shayee

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Compiler-generated communication for pipelined FPGA applications.

[BibT_eX]

[DOI]

Heidi E. Ziegler

Mary W. Hall

Proceedings of the 40th Design Automation Conference, 2003

Using estimates from behavioral synthesis tools in compiler-directed design space exploration.

[BibT_eX]

[DOI]

Byoungro So

Mary W. Hall

Proceedings of the 40th Design Automation Conference, 2003

2002

A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.

[BibT_eX]

[DOI]

Byoungro So

Mary W. Hall

Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Selector: A Language Construct for Developing Dynamic Applications.

[BibT_eX]

[DOI]

Bing Liu

Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

Data reorganization engines for the next generation of system-on-a-chip FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Coarse-Grain Pipelining on Multiple FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

Bridging the Gap between Compilation and Synthesis in the DEFACTO System.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2001

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Matching and searching analysis for parallel hardware implementation on FPGAs.

[BibT_eX]

[DOI]

Pablo Moisset

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

An External Memory Interface for FPGA-Based Computing Engines.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

A Behavioral Synthesis Estimation Interface for Configurable Computing.

[BibT_eX]

[DOI]

Ashok Venkatachar

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

Eliminating Synchronization Overhead in Automatically Parallelized Programs Using Dynamic Feedback.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 1999

Synchronization transformations for parallel computing.

[BibT_eX]

[DOI]

Concurr. Pract. Exp., 1999

Mapping Irregular Applications to DIVA, a PIM-based Data-Intensive Architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

DEFACTO: A Design Environment for Adaptive Computing Technology.

[BibT_eX]

[DOI]

Proceedings of the Parallel and Distributed Processing, 1999

Eliminating synchronization bottlenecks in object-based programs using adaptive replication.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Lock Coarsening: Eliminating Lock Overhead in Automatically Parallelized Object-Based Programs.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1998

1997

Commutativity Analysis: A New Analysis Technique for Parallelizing Compilers.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1997

On the Complexity of Commutativity Analysis.

[BibT_eX]

[DOI]

Oscar H. Ibarra

Int. J. Found. Comput. Sci., 1997

Dynamic Feedback: An Effective Technique for Adaptive Computing.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), 1997

1996

Commutativity Analysis: A New Analysis Framework for Parallelizing Compilers.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), 1996

Commutativity Analysis: A Technique for Automatically Parallelizing Pointer-Based Computations.

[BibT_eX]

[DOI]

Proceedings of IPPS '96, 1996

Semantic Foundations of Commutativity Analysis.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995

Scheduling Iterative Task Computation on Message-Passing Architectures.

[BibT_eX]

Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995

Efficient Parallelization of Relaxation Iterative Methods for Solving Banded Linear Systems on Multiprocessors.

[BibT_eX]