Pedram A. Riahi

According to our database, Pedram A. Riahi authored at least 5 papers between 2003 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A Flow Graph Technique for DFT Controller Modification.

Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2003

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.

Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the International Conference on Embedded Systems and Applications, 2003

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003