Payman Zarkesh-Ha
Orcid: 0000-0002-0571-9212
According to our database1,
Payman Zarkesh-Ha
authored at least 60 papers
between 1998 and 2024.
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Bibliography
2024
Energy-Efficient Neuromorphic Architectures for Nuclear Radiation Detection Applications.
Sensors, April, 2024
2023
Comput., April, 2023
Sensors, January, 2023
Medical Asset Management: Deep Learning Based Asset Usage Prediction in a Hospital Setting Using Real Data.
Proceedings of the International Conference on Machine Learning and Applications, 2023
A Subthreshold CMOS Inverter-Based Amplifier for Low Power and Low Noise Applications.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 13th IEEE Annual Computing and Communication Workshop and Conference, 2023
2022
Sensors, 2022
Cross-Correlation for Streaming Seismic Time Series to Detect Events using Parallel and Real-time Methods.
Proceedings of the 13th IEEE Annual Ubiquitous Computing, 2022
Proactive and Reactive Decision Based Agent Placement: Reliability and Latency Perspective.
Proceedings of the IEEE Global Communications Conference, 2022
Deep Reinforcement Learning for Online Latency Aware Workload Offloading in Mobile Edge Computing.
Proceedings of the IEEE Global Communications Conference, 2022
Classification of COVID-19 in Chest X-ray Images Using Fusion of Deep Features and LightGBM.
Proceedings of the 2022 IEEE World AI IoT Congress (AIIoT), 2022
2021
2020
5.2dB Sensitivity Enhancement in 25Gbps APD-Based Optical Receiver using Dynamic Biasing.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
J. Electronic Imaging, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
A meter-scale 600-Mb/s 2×2 imaging MIMO OOK VLC link using commercial LEDs and Si p-n photodiode array.
Proceedings of the 26th Wireless and Optical Communication Conference, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Analytical noise model for avalanche ISFET sensor suitable for Next Generation Sequencing.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 8-12, 2014, 2014
2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Reducing energy and increasing performance with traffic optimization in many-core systems.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011
2010
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Modeling NoC traffic locality and energy consumption with rent's communication probability distribution.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects.
J. Electron. Test., 2009
2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Prediction of interconnect adjacency distribution: derivation, validation, and applications.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004
2003
Prediction of interconnect pattern density distribution: derivation, validation, and applications.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
2000
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998