Payman Behnam

According to our database, Payman Behnam authored at least 35 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM.

Bingbing Li, Geng Yuan, Zigeng Wang, Shaoyi Huang, Hongwu Peng, Payman Behnam, Wujie Wen, Hang Liu, Caiwen Ding

CoRR, 2024

Harmonica: Hybrid Accelerator to Overcome Imperfections of Mixed-signal DNN Accelerators.

Payman Behnam, Uday Kamal, Ali Shafiee, Alexey Tumanov, Saibal Mukhopadhyay

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

SuperFedNAS: Cost-Efficient Federated Neural Architecture Search for On-device Inference.

Alind Khare, Animesh Agrawal, Aditya Annavajjala, Payman Behnam, Myungjin Lee, Hugo Latapie, Alexey Tumanov

Proceedings of the Computer Vision - ECCV 2024, 2024

2023

Hardware-Software Co-Design for Real-Time Latency-Accuracy Navigation in Tiny Machine Learning Applications.

Payman Behnam, Jianming Tong, Alind Khare, Yangyu Chen, Yue Pan, Pranav Gadikar, Abhimanyu Bambhaniya, Tushar Krishna, Alexey Tumanov

IEEE Micro, 2023

ABKD: Graph Neural Network Compression with Attention-Based Knowledge Distillation.

Anshul Ahluwalia, Rohit Das, Payman Behnam, Alind Khare, Pan Li, Alexey Tumanov

CoRR, 2023

Subgraph Stationary Hardware-Software Inference Co-Design.

Payman Behnam, Alexey Tumanov, Tushar Krishna, Pranav Gadikar, Yangyu Chen, Jianming Tong, Yue Pan, Abhimanyu Rajeshkumar Bambhaniya, Alind Khare

Proceedings of the Sixth Conference on Machine Learning and Systems, 2023

2022

Stereo: Assignment and Scheduling in MPSoC Under Process Variation by Combining Stochastic and Decomposition Approaches.

Behnam Khodabandeloo, Ahmad Khonsari, Payman Behnam, Alireza Majidi, Mohammad Hassan Hajiesmaili

IEEE Trans. Computers, 2022

Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory.

Payman Behnam, Mahdi Nazm Bojnordi

IEEE Trans. Computers, 2022

An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators.

Payman Behnam, Uday Kamal, Saibal Mukhopadhyay

CoRR, 2022

CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM.

Yixuan Luo, Payman Behnam, Kiran Thorat, Zhuo Liu, Hongwu Peng, Shaoyi Huang, Shu Zhou, Omer Khan, Alexey Tumanov, Caiwen Ding, Tong Geng

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.

Geng Yuan, Payman Behnam, Zhengang Li, Ali Shafiee, Sheng Lin, Xiaolong Ma, Hang Liu, Xuehai Qian, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators.

Geng Yuan, Payman Behnam, Yuxuan Cai, Ali Shafiee, Jingyan Fu, Zhiheng Liao, Zhengang Li, Xiaolong Ma, Jieren Deng, Jinhui Wang, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

STFL-DDR: Improving the Energy-Efficiency of Memory Interface.

Payman Behnam, Mahdi Nazm Bojnordi

IEEE Trans. Computers, 2020

RedCache: Reduced DRAM Caching.

Payman Behnam, Mahdi Nazm Bojnordi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.

Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling.

Payman Behnam, Mahdi Nazm Bojnordi

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell.

Yomi Karthik Rupesh, Payman Behnam, Goverdhan Reddy Pandla, Manikanth Miryala, Mahdi Nazm Bojnordi

IEEE Trans. Very Large Scale Integr. Syst., 2018

Validation of Hardware Security and Trust: A Survey.

Payman Behnam

CoRR, 2018

R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays.

Payman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines.

Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs.

Payman Behnam, Bijan Alizadeh, Sajjad Taheri

CoRR, 2017

Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures.

Payman Behnam, Naser Sedaghati, Mahdi Nazm Bojnordi

Proceedings of the 5th International Workshop on Energy Efficient Supercomputing, 2017

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach.

Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A novel SAT-based ATPG approach for transition delay faults.

Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

2016

High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters.

Eesa Nikahd, Payman Behnam, Reza Sameni

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Formally analyzing fault tolerance in datapath designs using equivalence checking.

Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.

Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan

IEEE Trans. Computers, 2015

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms.

Payman Behnam, Bijan Alizadeh

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism.

M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.

Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Hybrid history-based test overlapping to reduce test application time.

Vahid Janfaza, Bahjat Forouzandeh, Payman Behnam, Mohammadreza Najafi

Proceedings of the 2014 East-West Design & Test Symposium, 2014

Improving polynomial datapath debugging with HEDs.

Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

Automatic correction of certain design errors using mutation technique.

Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs.

Bijan Alizadeh, Payman Behnam

Microprocess. Microsystems, 2013

A probabilistic approach for counterexample generation to aid design debugging.

Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi

Proceedings of the East-West Design & Test Symposium, 2013