Pawan Sehgal
According to our database1,
Pawan Sehgal
authored at least 3 papers
in 2016.
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Bibliography
2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016