Pawan Sehgal

According to our database1, Pawan Sehgal authored at least 3 papers in 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
An effective and efficient algorithm to analyse and debug clock propagation issues.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016


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