Pawan Agarwal
Orcid: 0000-0003-4686-3170
According to our database1,
Pawan Agarwal
authored at least 13 papers
between 2010 and 2023.
Collaborative distances:
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Bibliography
2023
2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A New Boosted Active-Capacitor With Negative-G<sub>m</sub> for Wide Tuning Range VCOs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2019
A 25-35 GHz Neutralized Continuous Class-F CMOS Power Amplifier for 5G Mobile Communications Achieving 26% Modulation PAE at 1.5 Gb/s and 46.4% Peak PAE.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2014
On the Effects of Mismatch on Quadrature Accuracy in Tapped-Capacitor Load Independent Quadrature LC-Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Talking about code: Integrating pedagogical code reviews into early computing courses.
ACM Trans. Comput. Educ., 2013
2011
Proceedings of the 42nd ACM technical symposium on Computer science education, 2011
2010
A Socio-Psychological Approach to Improve Student Participation and Review Quality in Peer Code Reviews.
Proceedings of the IEEE Symposium on Visual Languages and Human-Centric Computing, 2010