Pavlos M. Mattheakis

According to our database, Pavlos M. Mattheakis authored at least 13 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV.

Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019

Timing-Driven and Placement-Aware Multibit Register Composition.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Accelerating Intercommunication in Highly Parallel Systems.

Nikolaos Tampouratzis, Pavlos M. Mattheakis, Ioannis Papaefstathiou

ACM Trans. Archit. Code Optim., 2016

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.

Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.

Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.

Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Hardware primitives for the synthesis of multithreaded elastic systems.

Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Logic synthesis of concurrent control specifications

Pavlos M. Mattheakis

PhD thesis, 2013

Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems.

Pavlos M. Mattheakis, Ioannis Papaefstathiou

ACM Trans. Archit. Code Optim., 2013

Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition.

Pavlos M. Mattheakis, Christos P. Sotiriou

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

A polynomial time flow for implementing free-choice Petri-nets.

Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2006

Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.

Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006