Pavel Benácek

According to our database, Pavel Benácek authored at least 12 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Scalable P4 Deparser for Speeds Over 100 Gbps.

Jakub Cabal, Pavel Benácek, Jana Foltova, Juraj Holub

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Accelerated DDoS Attacks Mitigation using Programmable Data Plane.

Mário Kuka, Kamil Vojanec, Jan Kucera, Pavel Benácek

Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018

P4-To-VHDL: Automatic generation of high-speed input and output network blocks.

Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka

Microprocess. Microsystems, 2018

Verification of Generated RTL from P4 Source Code.

Radek Isa, Pavel Benácek, Viktor Pus

Proceedings of the 2018 IEEE 26th International Conference on Network Protocols, 2018

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.

Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser.

Tomás Cejka, Petr Velan, Jirí Havránek, Pavel Benácek

Proceedings of the 12th International Conference on Autonomous Infrastructure, 2018

2017

Line rate programmable packet processing in 100Gb networks.

Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.

Pavel Benácek, Viktor Pus, Hana Kubátová

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2014

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.

Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Application specific processor with high level synthesized instructions (abstract only).

Viktor Pus, Pavel Benácek

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Architecture of Effective High-Speed Network Stream Merger.

Pavel Benácek, Hana Kubátová, Viktor Pus

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Change-point detection method on 100 Gb/s ethernet interface.

Pavel Benácek, Rudolf B. Blazek, Tomás Cejka, Hana Kubátová

Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014