Pavan Kumar Hanumolu
Orcid: 0000-0002-3456-2082Affiliations:
- University of Illinois, Urbana-Champaign, IL, USA
- Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA (PhD 2006)
According to our database1,
Pavan Kumar Hanumolu
authored at least 187 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C.
IEEE J. Solid State Circuits, December, 2023
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator.
IEEE J. Solid State Circuits, March, 2023
A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C.
IEEE J. Solid State Circuits, 2023
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
IEEE J. Solid State Circuits, 2022
A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors.
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
A 3.2-GHz 405 fs<sub>rms</sub> Jitter -237.2 dB FoM<sub>JIT</sub> Ring-Based Fractional-N Synthesizer.
IEEE J. Solid State Circuits, 2022
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022
2021
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications.
IEEE J. Solid State Circuits, 2021
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling.
IEEE J. Solid State Circuits, 2021
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques.
IEEE J. Solid State Circuits, 2020
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
3.2 A 0.0088mm<sup>2</sup> Resistor-Based Temperature Sensor Achieving 92fJ·K<sup>2</sup> FoM in 65nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Signal Processing Foundations for Time-Based Signal Representations: Neurobiological parallels to engineered systems designed for energy efficiency or hardware simplicity.
IEEE Signal Process. Mag., 2019
A 0.016 mm<sup>2</sup> 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.
IEEE J. Solid State Circuits, 2019
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers.
IEEE J. Solid State Circuits, 2019
A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Sel. Top. Signal Process., 2018
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.
IEEE J. Solid State Circuits, 2018
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes.
IEEE J. Solid State Circuits, 2018
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.
IEEE J. Solid State Circuits, 2018
A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier.
IEEE J. Solid State Circuits, 2018
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
F4: Emerging short-reach and high-density interconnect solutions for internet of everything.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques.
IEEE J. Solid State Circuits, 2014
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
Proceedings of the Symposium on VLSI Circuits, 2014
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control.
Proceedings of the Symposium on VLSI Circuits, 2012
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4<sup>th</sup>-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
IEEE J. Solid State Circuits, 2011
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits, 2011
A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique.
IEEE J. Solid State Circuits, 2011
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.
IEEE J. Solid State Circuits, 2011
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2011
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE J. Solid State Circuits, 2009
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture.
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Jitter in high-speed serial and parallel links.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003