Pavan Kumar
Affiliations:- Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA
- University of Victoria, BC, Canada (PhD 1996)
According to our database1,
Pavan Kumar
authored at least 5 papers
between 2014 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
Optimizing Convolutions for an Inference Accelerator: Case Study: Intel's NNP-I 1000 DL Compute Grid.
Proceedings of the AIMLSystems 2021: The First International Conference on AI-ML-Systems, Bangalore India, October 21, 2021
2018
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018
2017
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
A 0.4V∼1V 0.2A/mm<sup>2</sup> 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014