Paulo F. Butzen

According to our database, Paulo F. Butzen authored at least 61 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation.

Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen

Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Extending Multilevel ALS to Design ATMRs.

Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023

Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems.

Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen

J. Electron. Test., August, 2023

Effect of Unique Table Implementation in the Performance of BDD Packages.

Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures.

Cleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra, Paulo F. Butzen, Cristina Meinhardt

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

ATMR design by construction based on two-level ALS.

Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis.

Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

An Improved method to join BDDs for incompletely specified Boolean functions.

Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal.

Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Optimizing machine learning logic circuits with constant signal propagation.

Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen

Integr., 2022

A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations.

Cesar de S. Dias, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method.

Clayton R. Farias, Rafael B. Schvittz, Tiago R. Balen, Paulo F. Butzen

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

A Fast Approximate Function Generation Method to ATMR Architecture.

Guilherme B. Manske, Clayton R. Farias, Paulo F. Butzen, Leomar S. da Rosa

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Possible Reductions to Generate circuits from BDDs.

Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis.

Matheus F. Pontes, Ingrid F. V. Oliveira, Rafael B. Schvittz, Leomar Soares da Rosa Jr., Paulo F. Butzen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fault Tolerance Evaluation of Different Majority Voter Designs.

Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr., Paulo F. Butzen, Rafael Iankowski Soares

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions.

Cleiton Magano Marques, Cristina Meinhardt, Paulo Francisco Butzen

J. Electron. Test., 2021

Reliability Evaluation of Voters for Fault Tolerant Approximate Systems.

Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. de Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Benchmarking Open Access VLSI Partitioning Tools.

Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Soft Error Sensibility Window at FinFET DICE SRAM.

Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Soft Error Reliability of SRAM cells during the three operation states.

Cleiton Magano Marques, Cristina Meinhardt, Paulo F. Butzen

Proceedings of the IEEE Latin-American Test Symposium, 2020

Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients.

Rafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa

Proceedings of the IEEE International Test Conference, 2020

Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper.

Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.

Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates.

Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.

Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Reduction of neural network circuits by constant and nearly constant signal propagation.

Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

FBM: A Simple and Fast Algorithm for Placement Legalization.

Jorge Ferreira, Paulo F. Butzen, Cristina Meinhardt, Ricardo A. L. Reis

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Proposal and Evaluation of Pin Access Algorithms for Detailed Routing.

Marcelo Danigno, Paulo F. Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça, Ricardo Augusto da Luz Reis

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies.

Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fábio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt

Microelectron. Reliab., 2018

A Novel SPICE Model of Memristive Devices with Threshold Current Based Control.

Cesar de S. Dias, Paulo F. Butzen

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects.

Roberto B. Almeida, Paulo F. Butzen, Cristina Meinhardt

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Fault masking ratio analysis of majority voters topologies.

Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Reliability evaluation of circuits designed in multi- and single-stage versions.

Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt, Denis Teixeira Franco, Lirida A. B. Naviner, Leomar S. da Rosa, Paulo F. Butzen

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults.

Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits.

Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Exploring BDDs to reduce test pattern set.

Gabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.

Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, Y. Wang, Hao Cai

Microelectron. Reliab., 2016

Inserting permanent fault input dependence on PTM to improve robustness evaluation.

Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner, Cristina Meinhardt, Paulo F. Butzen

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A probabilistic model for stuck-on faults in combinational logic gates.

Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt, Paulo F. Butzen

Proceedings of the 17th Latin-American Test Symposium, 2016

Reliability analysis of majority voters under permanent faults.

Eduardo Liebl, Cristina Meinhardt, Paulo F. Butzen

Proceedings of the 17th Latin-American Test Symposium, 2016

PVT variability analysis of FinFET and CMOS XOR circuits at 16nm.

Fábio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

An Incremental Timing-Driven flow using quadratic formulation for detailed placement.

Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

An evaluation of BTI degradation of 32nm standard cells.

Rafael B. Schivittz, Cristina Meinhardt, Paulo F. Butzen

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Automatic circuit generation for sequential logic debug.

Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2013

BTI, HCI and TDDB aging impact in flip-flops.

Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2013

BTI and HCI first-order aging estimation for early use in standard cell technology mapping.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2013

A methodology to evaluate the aging impact on flip-flops performance.

Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2012

Design of CMOS logic gates with enhanced robustness against aging degradation.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2012

2011

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization.

John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim

IEEE Trans. Very Large Scale Integr. Syst., 2011

Area impact analysis of via-configurable regular fabric for digital integrated circuit design.

Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Impact and optimization of lithography-aware regular layout in digital circuit design.

Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Transistor network restructuring against NBTI degradation.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

Microelectron. Reliab., 2010

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.

Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas

Microelectron. J., 2010

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.

Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas

J. Low Power Electron., 2010

2009

Routing Resistance Influence in Loading Effect on Leakage Analysis.

Paulo F. Butzen, André Inácio Reis, Renato P. Ribas

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.

Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Modeling Subthreshold Leakage Current in General Transistor Networks.

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Modeling and estimating leakage current in series-parallel CMOS networks.

Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007