Paulo C. Santos

Orcid: 0000-0001-8555-2637

Affiliations:
  • Federal University of Rio Grande do Sul, Porto Alegre, Brazil


According to our database1, Paulo C. Santos authored at least 34 papers between 2012 and 2024.

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Bibliography

2024
HBPB, applying reuse distance to improve cache efficiency proactively.
J. Parallel Distributed Comput., 2024

Exploring compiler optimization space for control flow obfuscation.
Comput. Secur., 2024

Selecting the Best Compiler Optimization by Adopting Natural Language Processing.
IEEE Access, 2024

2023
Plug N' PIM: An integration strategy for Processing-in-Memory accelerators.
Integr., 2023

2022
Efficient Machine Learning execution with Near-Data Processing.
Microprocess. Microsystems, April, 2022

Sim2PIM: A complete simulation framework for Processing-in-Memory.
J. Syst. Archit., 2022

Vector In Memory Architecture for simple and high efficiency computing.
CoRR, 2022

SAPIVe: Simple AVX to PIM Vectorizer.
Proceedings of the XII Brazilian Symposium on Computing Systems Engineering, 2022

Avoiding Unnecessary Caching with History-Based Preemptive Bypassing.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

Advancing Near-Data Processing with Precise Exceptions and Efficient Data Fetching.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Aggressive Performance Improvement on Processing-in-Memory Devices by Adopting Hugepages.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021
Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions.
Int. J. Parallel Program., 2021

Machine Learning Migration for Efficient Near-Data Processing.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Sim2PIM: A Fast Method for Simulating Host Independent & PIM Agnostic Designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Providing Plug N' Play for Processing-in-Memory Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2019
A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation.
Microprocess. Microsystems, 2019

Skipping CNN Convolutions Through Efficient Memoization.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

The AV says: Your Hardware Definitions Were Updated!
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Exploring IoT platform with technologically agnostic processing-in-memory framework.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

HIPE: HMC instruction predication extension applied on database processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Processing in 3D memories to speed up operations on complex data structures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design space exploration for PIM architectures in 3D-stacked memories.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Operand size reconfiguration for big data processing in memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

NIM: An HMC-Based Machine for Neuron Computation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Large vector extensions inside the HMC.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Reconfigurable Vector Extensions inside the DRAM.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Opportunities and Challenges of Performing Vector Operations inside the DRAM.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

HMC and DDR Performance Trade-offs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

Saving memory movements through vector processing in the DRAM.
Proceedings of the 2015 International Conference on Compilers, 2015

2012
Adapting communication for adaptable processors: A multi-axis reconfiguration approach.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012


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