Paulino Ruiz-de-Clavijo

According to our database, Paulino Ruiz-de-Clavijo authored at least 26 papers between 2000 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Address-encoded byte order.

David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa

Microprocess. Microsystems, 2020

Using the complement of the cosine to compute trigonometric functions.

David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa

EURASIP J. Adv. Signal Process., 2020

2018

A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot.

Alejandro Carrasco, Jorge Ropero, Paulino Ruiz-de-Clavijo, Jaime Benjumea, Amalia Luque

Proceedings of the 2018 IEEE International Conference on Software Quality, 2018

2017

Minimalistic SDHC-SPI hardware reader module for boot loader applications.

Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos

Microelectron. J., 2017

2011

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation.

Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo

IEEE Trans. Instrum. Meas., 2011

Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells.

David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo

J. Low Power Electron., 2011

2010

Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies.

Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo

J. Low Power Electron., 2010

2008

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.

Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Improving the Performance of Static CMOS Gates by Using Independent Bodies.

David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo

J. Low Power Electron., 2007

Design of a FFT/IFFT module as an IP core suitable for embedded systems.

Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz

Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Static Power Consumption in CMOS Gates Using Independent Bodies.

David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006

Accurate Logic-Level Current Estimation for Digital CMOS Circuits.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo

J. Low Power Electron., 2006

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.

Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos

Proceedings of the International Symposium on Industrial Embedded Systems, 2006

2005

Logic-Level Fast Current Simulation for Digital CMOS Circuits.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design, 2005

Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.

Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo

Proceedings of the Integrated Circuit and System Design, 2005

2004

Signal Sampling Based Transition Modeling for Digital Gates Characterization.

Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa

Proceedings of the Integrated Circuit and System Design, 2004

2003

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.

David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán

Proceedings of the Integrated Circuit and System Design, 2003

Internode: Internal Node Logic Computational Model.

Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa

Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).

Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.

Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001

Gate-level simulation of CMOS circuits using the IDDM model.

Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

AUTODDM: automatic characterization tool for the delay degradation model.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.

Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Degradation Delay Model Extension to CMOS Gates.

Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit Design, 2000

Inertial and degradation delay model for CMOS logic gates.

Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000