Paul Xuanyuanliang Huang
Orcid: 0009-0001-8650-1222
According to our database1,
Paul Xuanyuanliang Huang
authored at least 6 papers
between 2022 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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2025
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2025
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2024
INTIACC: A Programmable Floating- Point Accelerator for Partial Differential Equations.
IEEE J. Solid State Circuits, September, 2024
IEEE J. Solid State Circuits, August, 2024
SPADES: A 0.54-GFLOPS/W Sparse Matrix Vector Multiplication Accelerator Featuring On-the-Fly GZIP Decompression for 3.36X Reduction in Off-Chip Data Movement.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
2023
iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022