Paul Vanoostende

According to our database1, Paul Vanoostende authored at least 6 papers between 1991 and 1995.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1991
1992
1993
1994
1995
0
1
2
3
1
1
1
2
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1995
On the use of VHDL-based behavioral synthesis for telecom ASIC design.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Issues in low-power design for telecom.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Design of a C-testable booth multiplier using a realistic fault model.
J. Electron. Test., 1994

Retargetable code generation: key issues for successful introduction.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993
Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators.
IEEE J. Solid State Circuits, January, 1993

1991
DARSI: RC data reduction [VLSI simulation].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991


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