Paul Scheffler

According to our database, Paul Scheffler authored at least 15 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A High-Performance, Energy-Efficient Modular DMA Engine Architecture.

Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini

IEEE Trans. Computers, January, 2024

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS.

Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. Gürkaynak, Luca Benini

CoRR, 2024

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak, Luca Benini

CoRR, 2024

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC.

Philippe Sauter, Thomas Benz, Paul Scheffler, Zerun Jiang, Beat Muheim, Frank K. Gürkaynak, Luca Benini

CoRR, 2024

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.

Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV.

Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers.

Paul Scheffler, Luca Colagrande, Luca Benini

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores.

Simone Manoni, Paul Scheffler, Alfio Di Mauro, Luca Zanatta, Andrea Acquaviva, Luca Benini, Andrea Bartolini

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra.

Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini

IEEE Trans. Parallel Distributed Syst., December, 2023

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.

Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads.

Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.

Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

Banshee: A Fast LLVM-Based RISC-V Binary Translator.

Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.

Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations.

Ines Schulze-Horn, Sabrina Hueren, Paul Scheffler, Holger Schiele

Appl. Artif. Intell., 2020