Paul R. Gray
According to our database1,
Paul R. Gray
authored at least 36 papers
between 1980 and 2006.
Collaborative distances:
Collaborative distances:
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE J. Solid State Circuits, 2004
2001
A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers.
IEEE J. Solid State Circuits, 2001
2000
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications.
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
1998
A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs].
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
Recent developments in high integration multi-standard CMOS transceivers for personal communication systems.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applications.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications.
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, March, 1995
IEEE J. Solid State Circuits, March, 1995
1994
IEEE J. Solid State Circuits, December, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
IEEE J. Solid State Circuits, December, 1993
A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS.
IEEE J. Solid State Circuits, December, 1993
A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels.
IEEE J. Solid State Circuits, April, 1993
IEEE J. Solid State Circuits, April, 1993
1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
1990
IEEE J. Solid State Circuits, December, 1990
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
IEEE J. Solid State Circuits, April, 1989
IEEE J. Solid State Circuits, February, 1989
1988
IEEE J. Solid State Circuits, December, 1988
IEEE J. Solid State Circuits, December, 1988
A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters.
IEEE J. Solid State Circuits, December, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
1980
IEEE Commun. Mag., 1980